diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index 4558518f..9152396e 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -418,7 +418,7 @@ INST(FCMLT_2,                "FCMLT (zero)",                              "01011
 INST(FCVTPS_2,               "FCVTPS (vector)",                           "010111101z100001101010nnnnnddddd")
 //INST(FCVTZS_int_1,           "FCVTZS (vector, integer)",                  "0101111011111001101110nnnnnddddd")
 INST(FCVTZS_int_2,           "FCVTZS (vector, integer)",                  "010111101z100001101110nnnnnddddd")
-//INST(FRECPE_1,               "FRECPE",                                    "0101111011111001110110nnnnnddddd")
+INST(FRECPE_1,               "FRECPE",                                    "0101111011111001110110nnnnnddddd")
 INST(FRECPE_2,               "FRECPE",                                    "010111101z100001110110nnnnnddddd")
 INST(FRECPX_1,               "FRECPX",                                    "0101111011111001111110nnnnnddddd")
 INST(FRECPX_2,               "FRECPX",                                    "010111101z100001111110nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
index 623a705c..5ec49844 100644
--- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
+++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
@@ -172,6 +172,16 @@ bool TranslatorVisitor::FCVTZU_int_2(bool sz, Vec Vn, Vec Vd) {
     return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, Signedness::Unsigned);
 }
 
+bool TranslatorVisitor::FRECPE_1(Vec Vn, Vec Vd) {
+    const size_t esize = 16;
+
+    const IR::U16 operand = V_scalar(esize, Vn);
+    const IR::U16 result = ir.FPRecipEstimate(operand);
+
+    V_scalar(esize, Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::FRECPE_2(bool sz, Vec Vn, Vec Vd) {
     const size_t esize = sz ? 64 : 32;