From 5ce187a54edef5c4d8e65c418296fd43bce13e02 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 2 Jun 2018 16:11:40 -0400 Subject: [PATCH] ir: Add opcodes for floating-point vector equalities --- .../emit_x64_vector_floating_point.cpp | 20 +++++++++++++++++++ src/frontend/ir/ir_emitter.cpp | 11 ++++++++++ src/frontend/ir/ir_emitter.h | 1 + src/frontend/ir/opcodes.inc | 2 ++ 4 files changed, 34 insertions(+) diff --git a/src/backend_x64/emit_x64_vector_floating_point.cpp b/src/backend_x64/emit_x64_vector_floating_point.cpp index 9f258145..89321454 100644 --- a/src/backend_x64/emit_x64_vector_floating_point.cpp +++ b/src/backend_x64/emit_x64_vector_floating_point.cpp @@ -189,6 +189,26 @@ void EmitX64::EmitFPVectorDiv64(EmitContext& ctx, IR::Inst* inst) { EmitVectorOperation64(code, ctx, inst, &Xbyak::CodeGenerator::divpd); } +void EmitX64::EmitFPVectorEqual32(EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]); + const Xbyak::Xmm b = ctx.reg_alloc.UseXmm(args[1]); + + code.cmpeqps(a, b); + + ctx.reg_alloc.DefineValue(inst, a); +} + +void EmitX64::EmitFPVectorEqual64(EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]); + const Xbyak::Xmm b = ctx.reg_alloc.UseXmm(args[1]); + + code.cmpeqpd(a, b); + + ctx.reg_alloc.DefineValue(inst, a); +} + void EmitX64::EmitFPVectorMul32(EmitContext& ctx, IR::Inst* inst) { EmitVectorOperation32(code, ctx, inst, &Xbyak::CodeGenerator::mulps); } diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index ba433755..1c74b0c0 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -1503,6 +1503,17 @@ U128 IREmitter::FPVectorDiv(size_t esize, const U128& a, const U128& b) { return {}; } +U128 IREmitter::FPVectorEqual(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 32: + return Inst(Opcode::FPVectorEqual32, a, b); + case 64: + return Inst(Opcode::FPVectorEqual64, a, b); + } + UNREACHABLE(); + return {}; +} + U128 IREmitter::FPVectorMul(size_t esize, const U128& a, const U128& b) { switch (esize) { case 32: diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index 629e21e7..78eebf80 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -274,6 +274,7 @@ public: U128 FPVectorAdd(size_t esize, const U128& a, const U128& b); U128 FPVectorDiv(size_t esize, const U128& a, const U128& b); + U128 FPVectorEqual(size_t esize, const U128& a, const U128& b); U128 FPVectorMul(size_t esize, const U128& a, const U128& b); U128 FPVectorSub(size_t esize, const U128& a, const U128& b); U128 FPVectorS32ToSingle(const U128& a); diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index 0a9470bc..6a8bde48 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -398,6 +398,8 @@ OPCODE(FPVectorAdd32, T::U128, T::U128, T::U OPCODE(FPVectorAdd64, T::U128, T::U128, T::U128 ) OPCODE(FPVectorDiv32, T::U128, T::U128, T::U128 ) OPCODE(FPVectorDiv64, T::U128, T::U128, T::U128 ) +OPCODE(FPVectorEqual32, T::U128, T::U128, T::U128 ) +OPCODE(FPVectorEqual64, T::U128, T::U128, T::U128 ) OPCODE(FPVectorMul32, T::U128, T::U128, T::U128 ) OPCODE(FPVectorMul64, T::U128, T::U128, T::U128 ) OPCODE(FPVectorS32ToSingle, T::U128, T::U128 )