From 65dcf45ca675b6bcf3d2ca000c4285bc266efa98 Mon Sep 17 00:00:00 2001 From: Mat M Date: Wed, 21 Sep 2016 12:51:13 -0400 Subject: [PATCH] FPSCR: Mask away reserved bits (#34) --- src/frontend/arm/FPSCR.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/frontend/arm/FPSCR.h b/src/frontend/arm/FPSCR.h index 825394c8..5335be9d 100644 --- a/src/frontend/arm/FPSCR.h +++ b/src/frontend/arm/FPSCR.h @@ -28,12 +28,12 @@ public: FPSCR() = default; FPSCR(const FPSCR&) = default; FPSCR(FPSCR&&) = default; - explicit FPSCR(u32 data) : value{data} {} + explicit FPSCR(u32 data) : value{data & mask} {} FPSCR& operator=(const FPSCR&) = default; FPSCR& operator=(FPSCR&&) = default; FPSCR& operator=(u32 data) { - value = data; + value = data & mask; return *this; } @@ -161,10 +161,10 @@ public: * - All exception enable bits are cleared. */ bool InRunFastMode() const { - constexpr u32 mask = 0x03001F00; - constexpr u32 expected = 0x03000000; + constexpr u32 runfast_mask = 0x03001F00; + constexpr u32 expected = 0x03000000; - return (value & mask) == expected; + return (value & runfast_mask) == expected; } /// Gets the underlying raw value within the FPSCR. @@ -173,6 +173,8 @@ public: } private: + // Bits 5-6, 13-14, and 19 are reserved. + static constexpr u32 mask = 0xFFF79F9F; u32 value = 0; };