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backend/A64: Use correct register size for EmitNot64

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This commit is contained in:
SachinVin 2019-10-06 11:20:25 +05:30
parent f8594f3bb9
commit 878db6d65d
1 changed files with 4 additions and 4 deletions
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8
src/backend/A64/emit_a64_data_processing.cpp
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@ -1056,11 +1056,11 @@ void EmitA64::EmitNot64(EmitContext& ctx, IR::Inst* inst) {
Arm64Gen::ARM64Reg result; Arm64Gen::ARM64Reg result;
if (args[0].IsImmediate()) { if (args[0].IsImmediate()) {
result = DecodeReg(ctx.reg_alloc.ScratchGpr()); result = ctx.reg_alloc.ScratchGpr();
code.MOVI2R(result, u32(~args[0].GetImmediateU32())); code.MOVI2R(result, u32(~args[0].GetImmediateU32()));
} }
else { else {
result = DecodeReg(ctx.reg_alloc.UseScratchGpr(args[0])); result = ctx.reg_alloc.UseScratchGpr(args[0]);
code.MVN(result, result); code.MVN(result, result);
} }
ctx.reg_alloc.DefineValue(inst, result); ctx.reg_alloc.DefineValue(inst, result);
@ -1116,12 +1116,12 @@ void EmitA64::EmitZeroExtendHalfToWord(EmitContext& ctx, IR::Inst* inst) {
} }
void EmitA64::EmitZeroExtendByteToLong(EmitContext& ctx, IR::Inst* inst) { void EmitA64::EmitZeroExtendByteToLong(EmitContext& ctx, IR::Inst* inst) {
// x64 zeros upper 32 bits on a 32-bit move // a64 zeros upper 32 bits on a 32-bit move
EmitZeroExtendByteToWord(ctx, inst); EmitZeroExtendByteToWord(ctx, inst);
} }
void EmitA64::EmitZeroExtendHalfToLong(EmitContext& ctx, IR::Inst* inst) { void EmitA64::EmitZeroExtendHalfToLong(EmitContext& ctx, IR::Inst* inst) {
// x64 zeros upper 32 bits on a 32-bit move // a64 zeros upper 32 bits on a 32-bit move
EmitZeroExtendHalfToWord(ctx, inst); EmitZeroExtendHalfToWord(ctx, inst);
} }