backend/A64: Use CSLE instead of branches for LSL LSR and ASR + minor cleanup
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SachinVin
parent
878db6d65d
commit
8c66a1609e
@ -19,7 +19,6 @@ void EmitA64::EmitPack2x32To1x64(EmitContext& ctx, IR::Inst* inst) {
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ARM64Reg lo = ctx.reg_alloc.UseScratchGpr(args[0]);
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ARM64Reg hi = ctx.reg_alloc.UseScratchGpr(args[1]);
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// code.MOV(lo, DecodeReg(lo)); // Zero extend to 64-bits
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code.ORR(lo, lo, hi, ArithOption{hi, ST_LSL, 32});
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ctx.reg_alloc.DefineValue(inst, lo);
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@ -98,7 +97,7 @@ void EmitA64::EmitIsZero64(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ARM64Reg result = ctx.reg_alloc.UseScratchGpr(args[0]);
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// TODO: Flag optimization
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code.CMP(result, WZR);
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code.CMP(result, ZR);
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code.CSET(result, CC_EQ);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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@ -231,8 +230,7 @@ void EmitA64::EmitLogicalShiftLeft32(EmitContext& ctx, IR::Inst* inst) {
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if (shift == 0) {
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// There is nothing more to do.
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} else if (shift < 32) {
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code.LSL(carry, result, shift - 1);
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code.LSR(carry, carry, 31);
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code.UBFX(carry, result, 32 - shift, 1);
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code.LSL(result, result, shift);
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} else if (shift > 32) {
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code.MOV(result, WZR);
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@ -246,44 +244,26 @@ void EmitA64::EmitLogicalShiftLeft32(EmitContext& ctx, IR::Inst* inst) {
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ctx.EraseInstruction(carry_inst);
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ctx.reg_alloc.DefineValue(inst, result);
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} else {
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//ctx.reg_alloc.Use(shift_arg, HostLoc::X0);
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Arm64Gen::ARM64Reg shift = DecodeReg(ctx.reg_alloc.UseScratchGpr(shift_arg));
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Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(operand_arg));
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Arm64Gen::ARM64Reg carry = DecodeReg(ctx.reg_alloc.UseScratchGpr(carry_arg));
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// TODO: Optimize this.
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// TODO: Use CSEL instead?
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FixupBranch Rs_gt32, Rs_eq32;
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std::vector<FixupBranch> end;
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FixupBranch end;
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code.ANDSI2R(shift, shift, 0xFF);
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// if (Rs & 0xFF == 0) goto end;
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end = code.B(CC_EQ);
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code.ANDI2R(shift, shift, 0xFF);
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code.CMP(shift, WZR);
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// if (Rs & 0xFF == 0) {
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end.push_back(code.B(CC_EQ));
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// }
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code.CMPI2R(shift, 32);
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Rs_gt32 = code.B(CC_GT);
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Rs_eq32 = code.B(CC_EQ);
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// } else if (Rs & 0xFF < 32) {
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code.SUBI2R(shift, shift, 1); // Subtract 1 to get the bit that is shiftedout, into the MSB.
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code.LSLV(result, result, shift);
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code.UBFX(carry, result, 31, 1);
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code.LSL(result, result, 1);
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end.push_back(code.B());
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// } else if (Rs & 0xFF > 32) {
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code.SetJumpTarget(Rs_gt32);
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code.MOV(result, WZR);
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code.MOV(carry, WZR);
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end.push_back(code.B());
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// } else if (Rs & 0xFF == 32) {
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code.SetJumpTarget(Rs_eq32);
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code.ANDI2R(carry, result, 1);
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code.MOV(result, WZR);
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// }
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for (FixupBranch e : end) {
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code.SetJumpTarget(e);
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}
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code.CSEL(result, result, WZR, CC_LT);
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code.CSEL(carry, carry, WZR, CC_LE);
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code.SetJumpTarget(end);
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ctx.reg_alloc.DefineValue(carry_inst, carry);
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ctx.EraseInstruction(carry_inst);
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@ -332,17 +312,16 @@ void EmitA64::EmitLogicalShiftRight32(EmitContext& ctx, IR::Inst* inst) {
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u8 shift = shift_arg.GetImmediateU8();
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if (shift <= 31) {
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code.LSR(result,result, shift);
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code.LSR(result, result, shift);
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} else {
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code.MOVI2R(result, 0);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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} else {
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//ctx.reg_alloc.Use(shift_arg, HostLoc::X0);
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Arm64Gen::ARM64Reg shift = DecodeReg(ctx.reg_alloc.UseScratchGpr(shift_arg));
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Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(operand_arg));
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// The 32-bit x64 SHR instruction masks the shift count by 0x1F before performing the shift.
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// The 32-bit A64 LSR instruction masks the shift count by 0x1F before performing the shift.
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// ARM differs from the behaviour: It does not mask the count, so shifts above 31 result in zeros.
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code.ANDI2R(shift, shift, 0xFF);
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@ -365,8 +344,7 @@ void EmitA64::EmitLogicalShiftRight32(EmitContext& ctx, IR::Inst* inst) {
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code.ANDI2R(carry, carry, 1);
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code.LSR(result,result, shift);
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} else if (shift == 32) {
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code.LSR(carry, result, 31);
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code.ANDI2R(carry, carry, 1);
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code.UBFX(carry, result, 31, 1);
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code.MOV(result, WZR);
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} else {
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code.MOV(result, WZR);
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@ -377,44 +355,27 @@ void EmitA64::EmitLogicalShiftRight32(EmitContext& ctx, IR::Inst* inst) {
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ctx.EraseInstruction(carry_inst);
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ctx.reg_alloc.DefineValue(inst, result);
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} else {
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//ctx.reg_alloc.Use(shift_arg, HostLoc::X0);
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Arm64Gen::ARM64Reg shift = DecodeReg(ctx.reg_alloc.UseScratchGpr(shift_arg));
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Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(operand_arg));
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Arm64Gen::ARM64Reg carry = DecodeReg(ctx.reg_alloc.UseScratchGpr(carry_arg));
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// TODO: Optimize this.
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// TODO: Use CSEL instead?
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FixupBranch Rs_gt32 , Rs_eq32;
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std::vector<FixupBranch> end;
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FixupBranch end;
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code.ANDI2R(shift, shift, 0xFF);
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code.CMPI2R(shift, 32);
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Rs_gt32 = code.B(CC_GT);
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Rs_eq32 = code.B(CC_EQ);
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code.ANDSI2R(shift, shift, 0xFF);
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// if (Rs & 0xFF == 0) goto end;
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code.CMP(shift, WZR);
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end.push_back(code.B(CC_EQ));
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// if (Rs & 0xFF <= 31) {
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end = code.B(CC_EQ);
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code.CMPI2R(shift, 32);
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code.SUBI2R(shift, shift, 1); // Subtract 1 to get the bit that is shifted out to the carry.
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code.LSRV(result, result, shift);
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code.ANDI2R(carry, result, 1);
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code.LSR(result, result, 1);
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end.push_back(code.B());
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// else if (Rs & 0xFF == 32) {
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code.SetJumpTarget(Rs_eq32);
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code.LSR(carry, result, 31);
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code.ANDI2R(carry, carry, 1);
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code.MOV(result, WZR);
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end.push_back(code.B());
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// } else if (Rs & 0xFF > 32) {
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code.SetJumpTarget(Rs_gt32);
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code.MOV(result, WZR);
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code.MOV(carry, WZR);
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// }
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for(FixupBranch e : end){
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code.SetJumpTarget(e);
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}
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code.CSEL(result, result, WZR, CC_LT);
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code.CSEL(carry, carry, WZR, CC_LE);
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code.SetJumpTarget(end);
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ctx.reg_alloc.DefineValue(carry_inst, carry);
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ctx.EraseInstruction(carry_inst);
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@ -474,7 +435,7 @@ void EmitA64::EmitArithmeticShiftRight32(EmitContext& ctx, IR::Inst* inst) {
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Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(operand_arg));
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Arm64Gen::ARM64Reg const31 = DecodeReg(ctx.reg_alloc.ScratchGpr());
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// The 32-bit arm64 SAR instruction masks the shift count by 0x1F before performing the shift.
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// The 32-bit arm64 ASR instruction masks the shift count by 0x1F before performing the shift.
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// ARM differs from the behaviour: It does not mask the count.
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// We note that all shift values above 31 have the same behaviour as 31 does, so we saturate `shift` to 31.
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@ -507,37 +468,28 @@ void EmitA64::EmitArithmeticShiftRight32(EmitContext& ctx, IR::Inst* inst) {
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ctx.EraseInstruction(carry_inst);
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ctx.reg_alloc.DefineValue(inst, result);
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} else {
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//ctx.reg_alloc.Use(shift_arg, HostLoc::X0);
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Arm64Gen::ARM64Reg shift = DecodeReg(ctx.reg_alloc.UseScratchGpr(shift_arg));
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Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(operand_arg));
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Arm64Gen::ARM64Reg carry = DecodeReg(ctx.reg_alloc.UseScratchGpr(carry_arg));
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// TODO: Optimize this.
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std::vector<FixupBranch> end;
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FixupBranch Rs_gt31;
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FixupBranch end;
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code.ANDI2R(shift, shift, 0xFF);
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code.CMPI2R(shift, u32(31));
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Rs_gt31 = code.B(CC_GT);
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code.ANDSI2R(shift, shift, 0xFF);
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// if (Rs & 0xFF == 0) goto end;
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code.CMP(shift, WZR);
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end.push_back(code.B(CC_EQ));
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// if (Rs & 0xFF <= 31) {
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end = code.B(CC_EQ);
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// else {
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code.MOVI2R(carry, 31);
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code.CMPI2R(shift, u32(31));
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code.CSEL(shift, shift, carry, CC_LE);
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code.SUBI2R(shift, shift, 1);
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code.ASRV(result, result, shift);
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code.ANDI2R(carry, result, 1);
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code.ASR(result, result, 1);
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end.push_back(code.B());
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// } else if (Rs & 0xFF > 31) {
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code.SetJumpTarget(Rs_gt31);
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code.ASR(result, result, 31); // 31 produces the same results as anything above 31
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code.ANDI2R(carry, result, 1);
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// }
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for (FixupBranch e : end) {
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code.SetJumpTarget(e);
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}
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code.SetJumpTarget(end);
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ctx.reg_alloc.DefineValue(carry_inst, carry);
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ctx.EraseInstruction(carry_inst);
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@ -594,11 +546,11 @@ void EmitA64::EmitRotateRight32(EmitContext& ctx, IR::Inst* inst) {
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ctx.reg_alloc.DefineValue(inst, result);
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} else {
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ctx.reg_alloc.Use(shift_arg, HostLoc::X0);
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Arm64Gen::ARM64Reg shift = DecodeReg(ctx.reg_alloc.UseGpr(shift_arg));
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Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(operand_arg));
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// aarch64 ROR instruction does (shift & 0x1F) for us.
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code.RORV(result, result, W0);
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code.RORV(result, result, shift);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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@ -622,7 +574,6 @@ void EmitA64::EmitRotateRight32(EmitContext& ctx, IR::Inst* inst) {
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ctx.EraseInstruction(carry_inst);
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ctx.reg_alloc.DefineValue(inst, result);
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} else {
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//ctx.reg_alloc.UseScratch(shift_arg, HostLoc::X0)
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Arm64Gen::ARM64Reg shift = DecodeReg(ctx.reg_alloc.UseScratchGpr(shift_arg));
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Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(operand_arg));
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Arm64Gen::ARM64Reg carry = DecodeReg(ctx.reg_alloc.UseScratchGpr(carry_arg));
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@ -634,7 +585,6 @@ void EmitA64::EmitRotateRight32(EmitContext& ctx, IR::Inst* inst) {
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code.ANDSI2R(shift, shift, u32(0xFF));
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// if (Rs & 0xFF == 0) goto end;
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code.CMP(shift, WZR);
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end.push_back(code.B(CC_EQ));
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code.ANDSI2R(shift, shift, u32(0x1F));
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zero_1F = code.B(CC_EQ);
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@ -695,7 +645,7 @@ void EmitA64::EmitRotateRightExtended(EmitContext& ctx, IR::Inst* inst) {
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code.MOV(temp, result);
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}
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// Set carry to the LSB and ROR
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// Set carry to the LSB and perform ROR.
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code.BFI(result, carry, 0, 1);
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code.ROR(result, result, 1);
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