diff --git a/src/frontend/disassembler/disassembler_arm.cpp b/src/frontend/disassembler/disassembler_arm.cpp index 1ca19045..636e10be 100644 --- a/src/frontend/disassembler/disassembler_arm.cpp +++ b/src/frontend/disassembler/disassembler_arm.cpp @@ -562,30 +562,30 @@ public: // Load/Store multiple instructions std::string arm_LDM(Cond cond, bool W, Reg n, RegList list) { - return fmt::format("ldm{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list); + return fmt::format("ldm{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", RegListToString(list)); } std::string arm_LDMDA(Cond cond, bool W, Reg n, RegList list) { - return fmt::format("ldmda{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list); + return fmt::format("ldmda{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", RegListToString(list)); } std::string arm_LDMDB(Cond cond, bool W, Reg n, RegList list) { - return fmt::format("ldmdb{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list); + return fmt::format("ldmdb{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", RegListToString(list)); } std::string arm_LDMIB(Cond cond, bool W, Reg n, RegList list) { - return fmt::format("ldmib{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list); + return fmt::format("ldmib{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", RegListToString(list)); } std::string arm_LDM_usr() { return "ice"; } std::string arm_LDM_eret() { return "ice"; } std::string arm_STM(Cond cond, bool W, Reg n, RegList list) { - return fmt::format("stm{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list); + return fmt::format("stm{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", RegListToString(list)); } std::string arm_STMDA(Cond cond, bool W, Reg n, RegList list) { - return fmt::format("stmda{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list); + return fmt::format("stmda{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", RegListToString(list)); } std::string arm_STMDB(Cond cond, bool W, Reg n, RegList list) { - return fmt::format("stmdb{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list); + return fmt::format("stmdb{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", RegListToString(list)); } std::string arm_STMIB(Cond cond, bool W, Reg n, RegList list) { - return fmt::format("stmib{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", list); + return fmt::format("stmib{} {}{}, {{{}}}", CondToString(cond), n, W ? "!" : "", RegListToString(list)); } std::string arm_STM_usr() { return "ice"; } diff --git a/src/frontend/disassembler/disassembler_thumb.cpp b/src/frontend/disassembler/disassembler_thumb.cpp index 149605f0..769a06ee 100644 --- a/src/frontend/disassembler/disassembler_thumb.cpp +++ b/src/frontend/disassembler/disassembler_thumb.cpp @@ -262,12 +262,12 @@ public: std::string thumb16_PUSH(bool M, RegList reg_list) { if (M) reg_list |= 1 << 14; - return fmt::format("push {}", reg_list); + return fmt::format("push {{{}}}", RegListToString(reg_list)); } std::string thumb16_POP(bool P, RegList reg_list) { if (P) reg_list |= 1 << 15; - return fmt::format("pop {}", reg_list); + return fmt::format("pop {{{}}}", RegListToString(reg_list)); } std::string thumb16_SETEND(bool E) { @@ -291,12 +291,12 @@ public: } std::string thumb16_STMIA(Reg n, RegList reg_list) { - return fmt::format("stm {}!, {}", n, reg_list); + return fmt::format("stm {}!, {{{}}}", n, RegListToString(reg_list)); } std::string thumb16_LDMIA(Reg n, RegList reg_list) { bool write_back = !Common::Bit(static_cast(n), reg_list); - return fmt::format("ldm {}{}, {}", n, write_back ? "!" : "", reg_list); + return fmt::format("ldm {}{}, {{{}}}", n, write_back ? "!" : "", RegListToString(reg_list)); } std::string thumb16_BX(Reg m) { diff --git a/tests/arm/test_arm_disassembler.cpp b/tests/arm/test_arm_disassembler.cpp index 680372ac..d81d48cb 100644 --- a/tests/arm/test_arm_disassembler.cpp +++ b/tests/arm/test_arm_disassembler.cpp @@ -376,3 +376,7 @@ TEST_CASE("Disassemble synchronization primitive instructions", "[arm][disassemb REQUIRE(DisassembleArm(0xE1031092) == "swp r1, r2, [r3]"); REQUIRE(DisassembleArm(0xE1431092) == "swpb r1, r2, [r3]"); } + +TEST_CASE("Disassemble load / store multiple instructions", "[arm][disassembler]") { + REQUIRE(DisassembleArm(0xE92D500F) == "stmdb sp!, {r0, r1, r2, r3, r12, lr}"); +}