From b1a8c39c192c6ec40ca7d6a66735c0d24d0a769f Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sat, 13 Jan 2018 18:01:43 +0000 Subject: [PATCH] A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31 --- .../A64/translate/impl/data_processing_addsub.cpp | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/src/frontend/A64/translate/impl/data_processing_addsub.cpp b/src/frontend/A64/translate/impl/data_processing_addsub.cpp index 947b61d8..34059040 100644 --- a/src/frontend/A64/translate/impl/data_processing_addsub.cpp +++ b/src/frontend/A64/translate/impl/data_processing_addsub.cpp @@ -224,11 +224,7 @@ bool TranslatorVisitor::ADDS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Re ir.SetNZCV(ir.NZCVFrom(result)); - if (Rd == Reg::SP) { - SP(datasize, result); - } else { - X(datasize, Rd, result); - } + X(datasize, Rd, result); return true; } @@ -264,11 +260,7 @@ bool TranslatorVisitor::SUBS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Re ir.SetNZCV(ir.NZCVFrom(result)); - if (Rd == Reg::SP) { - SP(datasize, result); - } else { - X(datasize, Rd, result); - } + X(datasize, Rd, result); return true; }