diff --git a/src/frontend/A32/translate/translate_thumb.cpp b/src/frontend/A32/translate/translate_thumb.cpp
index 7f9a3fcc..e6e36e25 100644
--- a/src/frontend/A32/translate/translate_thumb.cpp
+++ b/src/frontend/A32/translate/translate_thumb.cpp
@@ -38,11 +38,12 @@ struct ThumbTranslatorVisitor final {
         return false;
     }
 
+    // LSLS <Rd>, <Rm>, #<imm5>
     bool thumb16_LSL_imm(Imm5 imm5, Reg m, Reg d) {
-        u8 shift_n = imm5;
-        // LSLS <Rd>, <Rm>, #<imm5>
-        auto cpsr_c = ir.GetCFlag();
-        auto result = ir.LogicalShiftLeft(ir.GetRegister(m), ir.Imm8(shift_n), cpsr_c);
+        const u8 shift_n = imm5;
+        const auto cpsr_c = ir.GetCFlag();
+        const auto result = ir.LogicalShiftLeft(ir.GetRegister(m), ir.Imm8(shift_n), cpsr_c);
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -50,11 +51,12 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // LSRS <Rd>, <Rm>, #<imm5>
     bool thumb16_LSR_imm(Imm5 imm5, Reg m, Reg d) {
-        u8 shift_n = imm5 != 0 ? imm5 : 32;
-        // LSRS <Rd>, <Rm>, #<imm5>
-        auto cpsr_c = ir.GetCFlag();
-        auto result = ir.LogicalShiftRight(ir.GetRegister(m), ir.Imm8(shift_n), cpsr_c);
+        const u8 shift_n = imm5 != 0 ? imm5 : 32;
+        const auto cpsr_c = ir.GetCFlag();
+        const auto result = ir.LogicalShiftRight(ir.GetRegister(m), ir.Imm8(shift_n), cpsr_c);
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -62,11 +64,12 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // ASRS <Rd>, <Rm>, #<imm5>
     bool thumb16_ASR_imm(Imm5 imm5, Reg m, Reg d) {
-        u8 shift_n = imm5 != 0 ? imm5 : 32;
-        // ASRS <Rd>, <Rm>, #<imm5>
-        auto cpsr_c = ir.GetCFlag();
-        auto result = ir.ArithmeticShiftRight(ir.GetRegister(m), ir.Imm8(shift_n), cpsr_c);
+        const u8 shift_n = imm5 != 0 ? imm5 : 32;
+        const auto cpsr_c = ir.GetCFlag();
+        const auto result = ir.ArithmeticShiftRight(ir.GetRegister(m), ir.Imm8(shift_n), cpsr_c);
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -74,10 +77,10 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // ADDS <Rd>, <Rn>, <Rm>
+    // Note that it is not possible to encode Rd == R15.
     bool thumb16_ADD_reg_t1(Reg m, Reg n, Reg d) {
-        // ADDS <Rd>, <Rn>, <Rm>
-        // Note that it is not possible to encode Rd == R15.
-        auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(0));
+        const auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(0));
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -86,10 +89,10 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // SUBS <Rd>, <Rn>, <Rm>
+    // Note that it is not possible to encode Rd == R15.
     bool thumb16_SUB_reg(Reg m, Reg n, Reg d) {
-        // SUBS <Rd>, <Rn>, <Rm>
-        // Note that it is not possible to encode Rd == R15.
-        auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(1));
+        const auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(1));
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -98,11 +101,12 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // ADDS <Rd>, <Rn>, #<imm3>
+    // Rd can never encode R15.
     bool thumb16_ADD_imm_t1(Imm3 imm3, Reg n, Reg d) {
-        u32 imm32 = imm3 & 0x7;
-        // ADDS <Rd>, <Rn>, #<imm3>
-        // Rd can never encode R15.
-        auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(0));
+        const u32 imm32 = imm3 & 0x7;
+        const auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(0));
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -111,11 +115,12 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // SUBS <Rd>, <Rn>, #<imm3>
+    // Rd can never encode R15.
     bool thumb16_SUB_imm_t1(Imm3 imm3, Reg n, Reg d) {
-        u32 imm32 = imm3 & 0x7;
-        // SUBS <Rd>, <Rn>, #<imm3>
-        // Rd can never encode R15.
-        auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
+        const u32 imm32 = imm3 & 0x7;
+        const auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -124,21 +129,23 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // MOVS <Rd>, #<imm8>
+    // Rd can never encode R15.
     bool thumb16_MOV_imm(Reg d, Imm8 imm8) {
-        u32 imm32 = imm8 & 0xFF;
-        // MOVS <Rd>, #<imm8>
-        // Rd can never encode R15.
-        auto result = ir.Imm32(imm32);
+        const u32 imm32 = imm8 & 0xFF;
+        const auto result = ir.Imm32(imm32);
+
         ir.SetRegister(d, result);
         ir.SetNFlag(ir.MostSignificantBit(result));
         ir.SetZFlag(ir.IsZero(result));
         return true;
     }
 
+    // CMP <Rn>, #<imm8>
     bool thumb16_CMP_imm(Reg n, Imm8 imm8) {
-        u32 imm32 = imm8 & 0xFF;
-        // CMP <Rn>, #<imm8>
-        auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
+        const u32 imm32 = imm8 & 0xFF;
+        const auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
+
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
         ir.SetCFlag(result.carry);
@@ -146,12 +153,14 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // ADDS <Rdn>, #<imm8>
+    // Rd can never encode R15.
     bool thumb16_ADD_imm_t2(Reg d_n, Imm8 imm8) {
-        u32 imm32 = imm8 & 0xFF;
-        Reg d = d_n, n = d_n;
-        // ADDS <Rdn>, #<imm8>
-        // Rd can never encode R15.
-        auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(0));
+        const u32 imm32 = imm8 & 0xFF;
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(0));
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -160,12 +169,14 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // SUBS <Rd>, <Rn>, #<imm3>
+    // Rd can never encode R15.
     bool thumb16_SUB_imm_t2(Reg d_n, Imm8 imm8) {
-        u32 imm32 = imm8 & 0xFF;
-        Reg d = d_n, n = d_n;
-        // SUBS <Rd>, <Rn>, #<imm3>
-        // Rd can never encode R15.
-        auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
+        const u32 imm32 = imm8 & 0xFF;
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -174,34 +185,40 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // ANDS <Rdn>, <Rm>
+    // Note that it is not possible to encode Rdn == R15.
     bool thumb16_AND_reg(Reg m, Reg d_n) {
-        const Reg d = d_n, n = d_n;
-        // ANDS <Rdn>, <Rm>
-        // Note that it is not possible to encode Rdn == R15.
-        auto result = ir.And(ir.GetRegister(n), ir.GetRegister(m));
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto result = ir.And(ir.GetRegister(n), ir.GetRegister(m));
+
         ir.SetRegister(d, result);
         ir.SetNFlag(ir.MostSignificantBit(result));
         ir.SetZFlag(ir.IsZero(result));
         return true;
     }
 
+    // EORS <Rdn>, <Rm>
+    // Note that it is not possible to encode Rdn == R15.
     bool thumb16_EOR_reg(Reg m, Reg d_n) {
-        const Reg d = d_n, n = d_n;
-        // EORS <Rdn>, <Rm>
-        // Note that it is not possible to encode Rdn == R15.
-        auto result = ir.Eor(ir.GetRegister(n), ir.GetRegister(m));
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto result = ir.Eor(ir.GetRegister(n), ir.GetRegister(m));
+
         ir.SetRegister(d, result);
         ir.SetNFlag(ir.MostSignificantBit(result));
         ir.SetZFlag(ir.IsZero(result));
         return true;
     }
 
+    // LSLS <Rdn>, <Rm>
     bool thumb16_LSL_reg(Reg m, Reg d_n) {
-        const Reg d = d_n, n = d_n;
-        // LSLS <Rdn>, <Rm>
-        auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
-        auto apsr_c = ir.GetCFlag();
-        auto result_carry = ir.LogicalShiftLeft(ir.GetRegister(n), shift_n, apsr_c);
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
+        const auto apsr_c = ir.GetCFlag();
+        const auto result_carry = ir.LogicalShiftLeft(ir.GetRegister(n), shift_n, apsr_c);
+
         ir.SetRegister(d, result_carry.result);
         ir.SetNFlag(ir.MostSignificantBit(result_carry.result));
         ir.SetZFlag(ir.IsZero(result_carry.result));
@@ -209,12 +226,14 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // LSRS <Rdn>, <Rm>
     bool thumb16_LSR_reg(Reg m, Reg d_n) {
-        const Reg d = d_n, n = d_n;
-        // LSRS <Rdn>, <Rm>
-        auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
-        auto cpsr_c = ir.GetCFlag();
-        auto result = ir.LogicalShiftRight(ir.GetRegister(n), shift_n, cpsr_c);
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
+        const auto cpsr_c = ir.GetCFlag();
+        const auto result = ir.LogicalShiftRight(ir.GetRegister(n), shift_n, cpsr_c);
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -222,12 +241,14 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // ASRS <Rdn>, <Rm>
     bool thumb16_ASR_reg(Reg m, Reg d_n) {
-        const Reg d = d_n, n = d_n;
-        // ASRS <Rdn>, <Rm>
-        auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
-        auto cpsr_c = ir.GetCFlag();
-        auto result = ir.ArithmeticShiftRight(ir.GetRegister(n), shift_n, cpsr_c);
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
+        const auto cpsr_c = ir.GetCFlag();
+        const auto result = ir.ArithmeticShiftRight(ir.GetRegister(n), shift_n, cpsr_c);
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -235,12 +256,14 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // ADCS <Rdn>, <Rm>
+    // Note that it is not possible to encode Rd == R15.
     bool thumb16_ADC_reg(Reg m, Reg d_n) {
-        Reg d = d_n, n = d_n;
-        // ADCS <Rdn>, <Rm>
-        // Note that it is not possible to encode Rd == R15.
-        auto aspr_c = ir.GetCFlag();
-        auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), aspr_c);
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto aspr_c = ir.GetCFlag();
+        const auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), aspr_c);
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -249,12 +272,14 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // SBCS <Rdn>, <Rm>
+    // Note that it is not possible to encode Rd == R15.
     bool thumb16_SBC_reg(Reg m, Reg d_n) {
-        Reg d = d_n, n = d_n;
-        // SBCS <Rdn>, <Rm>
-        // Note that it is not possible to encode Rd == R15.
-        auto aspr_c = ir.GetCFlag();
-        auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), aspr_c);
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto aspr_c = ir.GetCFlag();
+        const auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), aspr_c);
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -263,12 +288,14 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // RORS <Rdn>, <Rm>
     bool thumb16_ROR_reg(Reg m, Reg d_n) {
-        Reg d = d_n, n = d_n;
-        // RORS <Rdn>, <Rm>
-        auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
-        auto cpsr_c = ir.GetCFlag();
-        auto result = ir.RotateRight(ir.GetRegister(n), shift_n, cpsr_c);
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
+        const auto cpsr_c = ir.GetCFlag();
+        const auto result = ir.RotateRight(ir.GetRegister(n), shift_n, cpsr_c);
+
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -276,18 +303,18 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // TST <Rn>, <Rm>
     bool thumb16_TST_reg(Reg m, Reg n) {
-        // TST <Rn>, <Rm>
-        auto result = ir.And(ir.GetRegister(n), ir.GetRegister(m));
+        const auto result = ir.And(ir.GetRegister(n), ir.GetRegister(m));
         ir.SetNFlag(ir.MostSignificantBit(result));
         ir.SetZFlag(ir.IsZero(result));
         return true;
     }
 
+    // RSBS <Rd>, <Rn>, #0
+    // Rd can never encode R15.
     bool thumb16_RSB_imm(Reg n, Reg d) {
-        // RSBS <Rd>, <Rn>, #0
-        // Rd can never encode R15.
-        auto result = ir.SubWithCarry(ir.Imm32(0), ir.GetRegister(n), ir.Imm1(1));
+        const auto result = ir.SubWithCarry(ir.Imm32(0), ir.GetRegister(n), ir.Imm1(1));
         ir.SetRegister(d, result.result);
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
@@ -296,9 +323,9 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // CMP <Rn>, <Rm>
     bool thumb16_CMP_reg_t1(Reg m, Reg n) {
-        // CMP <Rn>, <Rm>
-        auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(1));
+        const auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(1));
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
         ir.SetCFlag(result.carry);
@@ -306,9 +333,9 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // CMN <Rn>, <Rm>
     bool thumb16_CMN_reg(Reg m, Reg n) {
-        // CMN <Rn>, <Rm>
-        auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(0));
+        const auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(0));
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
         ir.SetCFlag(result.carry);
@@ -316,57 +343,65 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // ORRS <Rdn>, <Rm>
+    // Rd cannot encode R15.
     bool thumb16_ORR_reg(Reg m, Reg d_n) {
-        Reg d = d_n, n = d_n;
-        // ORRS <Rdn>, <Rm>
-        // Rd cannot encode R15.
-        auto result = ir.Or(ir.GetRegister(m), ir.GetRegister(n));
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto result = ir.Or(ir.GetRegister(m), ir.GetRegister(n));
+
         ir.SetRegister(d, result);
         ir.SetNFlag(ir.MostSignificantBit(result));
         ir.SetZFlag(ir.IsZero(result));
         return true;
     }
 
+    // MULS <Rdn>, <Rm>, <Rdn>
+    // Rd cannot encode R15.
     bool thumb16_MUL_reg(Reg n, Reg d_m) {
-        Reg d = d_m, m = d_m;
-        // MULS <Rdn>, <Rm>, <Rdn>
-        // Rd cannot encode R15.
-        auto result = ir.Mul(ir.GetRegister(m), ir.GetRegister(n));
+        const Reg d = d_m;
+        const Reg m = d_m;
+        const auto result = ir.Mul(ir.GetRegister(m), ir.GetRegister(n));
+
         ir.SetRegister(d, result);
         ir.SetNFlag(ir.MostSignificantBit(result));
         ir.SetZFlag(ir.IsZero(result));
         return true;
     }
 
+    // BICS <Rdn>, <Rm>
+    // Rd cannot encode R15.
     bool thumb16_BIC_reg(Reg m, Reg d_n) {
-        Reg d = d_n, n = d_n;
-        // BICS <Rdn>, <Rm>
-        // Rd cannot encode R15.
-        auto result = ir.And(ir.GetRegister(n), ir.Not(ir.GetRegister(m)));
+        const Reg d = d_n;
+        const Reg n = d_n;
+        const auto result = ir.And(ir.GetRegister(n), ir.Not(ir.GetRegister(m)));
+
         ir.SetRegister(d, result);
         ir.SetNFlag(ir.MostSignificantBit(result));
         ir.SetZFlag(ir.IsZero(result));
         return true;
     }
 
+    // MVNS <Rd>, <Rm>
+    // Rd cannot encode R15.
     bool thumb16_MVN_reg(Reg m, Reg d) {
-        // MVNS <Rd>, <Rm>
-        // Rd cannot encode R15.
-        auto result = ir.Not(ir.GetRegister(m));
+        const auto result = ir.Not(ir.GetRegister(m));
         ir.SetRegister(d, result);
         ir.SetNFlag(ir.MostSignificantBit(result));
         ir.SetZFlag(ir.IsZero(result));
         return true;
     }
 
+    // ADD <Rdn>, <Rm>
     bool thumb16_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
-        Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
-        Reg d = d_n, n = d_n;
+        const Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
+        const Reg n = d_n;
         if (n == Reg::PC && m == Reg::PC) {
             return UnpredictableInstruction();
         }
-        // ADD <Rdn>, <Rm>
-        auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(0));
+
+        const Reg d = d_n;
+        const auto result = ir.AddWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(0));
         if (d == Reg::PC) {
             ir.ALUWritePC(result.result);
             // Return to dispatch as we can't predict what PC is going to be. Stop compilation.
@@ -378,15 +413,17 @@ struct ThumbTranslatorVisitor final {
         }
     }
 
+    // CMP <Rn>, <Rm>
     bool thumb16_CMP_reg_t2(bool n_hi, Reg m, Reg n_lo) {
-        Reg n = n_hi ? (n_lo + 8) : n_lo;
+        const Reg n = n_hi ? (n_lo + 8) : n_lo;
         if (n < Reg::R8 && m < Reg::R8) {
             return UnpredictableInstruction();
-        } else if (n == Reg::PC || m == Reg::PC) {
+        }
+        if (n == Reg::PC || m == Reg::PC) {
             return UnpredictableInstruction();
         }
-        // CMP <Rn>, <Rm>
-        auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(1));
+
+        const auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), ir.Imm1(1));
         ir.SetNFlag(ir.MostSignificantBit(result.result));
         ir.SetZFlag(ir.IsZero(result.result));
         ir.SetCFlag(result.carry);
@@ -394,10 +431,11 @@ struct ThumbTranslatorVisitor final {
         return true;
     }
 
+    // MOV <Rd>, <Rm>
     bool thumb16_MOV_reg(bool d_hi, Reg m, Reg d_lo) {
-        Reg d = d_hi ? (d_lo + 8) : d_lo;
-        // MOV <Rd>, <Rm>
-        auto result = ir.GetRegister(m);
+        const Reg d = d_hi ? (d_lo + 8) : d_lo;
+        const auto result = ir.GetRegister(m);
+
         if (d == Reg::PC) {
             ir.ALUWritePC(result);
             ir.SetTerm(IR::Term::FastDispatchHint{});
@@ -408,276 +446,305 @@ struct ThumbTranslatorVisitor final {
         }
     }
 
+    // LDR <Rt>, <label>
+    // Rt cannot encode R15.
     bool thumb16_LDR_literal(Reg t, Imm8 imm8) {
-        u32 imm32 = imm8 << 2;
-        // LDR <Rt>, <label>
-        // Rt cannot encode R15.
-        u32 address = ir.AlignPC(4) + imm32;
-        auto data = ir.ReadMemory32(ir.Imm32(address));
+        const u32 imm32 = imm8 << 2;
+        const u32 address = ir.AlignPC(4) + imm32;
+        const auto data = ir.ReadMemory32(ir.Imm32(address));
+
         ir.SetRegister(t, data);
         return true;
     }
 
+    // STR <Rt>, [<Rn>, <Rm>]
+    // Rt cannot encode R15.
     bool thumb16_STR_reg(Reg m, Reg n, Reg t) {
-        // STR <Rt>, [<Rn>, <Rm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
-        auto data = ir.GetRegister(t);
+        const auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
+        const auto data = ir.GetRegister(t);
+
         ir.WriteMemory32(address, data);
         return true;
     }
 
+    // STRH <Rt>, [<Rn>, <Rm>]
+    // Rt cannot encode R15.
     bool thumb16_STRH_reg(Reg m, Reg n, Reg t) {
-        // STRH <Rt>, [<Rn>, <Rm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
-        auto data = ir.LeastSignificantHalf(ir.GetRegister(t));
+        const auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
+        const auto data = ir.LeastSignificantHalf(ir.GetRegister(t));
+
         ir.WriteMemory16(address, data);
         return true;
     }
 
+    // STRB <Rt>, [<Rn>, <Rm>]
+    // Rt cannot encode R15.
     bool thumb16_STRB_reg(Reg m, Reg n, Reg t) {
-        // STRB <Rt>, [<Rn>, <Rm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
-        auto data = ir.LeastSignificantByte(ir.GetRegister(t));
+        const auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
+        const auto data = ir.LeastSignificantByte(ir.GetRegister(t));
+
         ir.WriteMemory8(address, data);
         return true;
     }
 
+    // LDRSB <Rt>, [<Rn>, <Rm>]
+    // Rt cannot encode R15.
     bool thumb16_LDRSB_reg(Reg m, Reg n, Reg t) {
-        // LDRSB <Rt>, [<Rn>, <Rm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
-        auto data = ir.SignExtendByteToWord(ir.ReadMemory8(address));
+        const auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
+        const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(address));
+
         ir.SetRegister(t, data);
         return true;
     }
 
+    // LDR <Rt>, [<Rn>, <Rm>]
+    // Rt cannot encode R15.
     bool thumb16_LDR_reg(Reg m, Reg n, Reg t) {
-        // LDR <Rt>, [<Rn>, <Rm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
-        auto data = ir.ReadMemory32(address);
+        const auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
+        const auto data = ir.ReadMemory32(address);
+
         ir.SetRegister(t, data);
         return true;
     }
 
+    // LDRH <Rt>, [<Rn>, <Rm>]
+    // Rt cannot encode R15.
     bool thumb16_LDRH_reg(Reg m, Reg n, Reg t) {
-        // LDRH <Rt>, [<Rn>, <Rm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
-        auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(address));
+        const auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
+        const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(address));
+
         ir.SetRegister(t, data);
         return true;
     }
 
+    // LDRB <Rt>, [<Rn>, <Rm>]
+    // Rt cannot encode R15.
     bool thumb16_LDRB_reg(Reg m, Reg n, Reg t) {
-        // LDRB <Rt>, [<Rn>, <Rm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
-        auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
+        const auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
+        const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
+
         ir.SetRegister(t, data);
         return true;
     }
 
+    // LDRH <Rt>, [<Rn>, <Rm>]
+    // Rt cannot encode R15.
     bool thumb16_LDRSH_reg(Reg m, Reg n, Reg t) {
-        // LDRH <Rt>, [<Rn>, <Rm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
-        auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(address));
+        const auto address = ir.Add(ir.GetRegister(n), ir.GetRegister(m));
+        const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(address));
+
         ir.SetRegister(t, data);
         return true;
     }
 
+    // STR <Rt>, [<Rn>, #<imm>]
+    // Rt cannot encode R15.
     bool thumb16_STR_imm_t1(Imm5 imm5, Reg n, Reg t) {
-        u32 imm32 = imm5 << 2;
-        // STR <Rt>, [<Rn>, #<imm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
-        auto data = ir.GetRegister(t);
+        const u32 imm32 = imm5 << 2;
+        const auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
+        const auto data = ir.GetRegister(t);
+
         ir.WriteMemory32(address, data);
         return true;
     }
 
+    // LDR <Rt>, [<Rn>, #<imm>]
+    // Rt cannot encode R15.
     bool thumb16_LDR_imm_t1(Imm5 imm5, Reg n, Reg t) {
-        u32 imm32 = imm5 << 2;
-        // LDR <Rt>, [<Rn>, #<imm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
-        auto data = ir.ReadMemory32(address);
+        const u32 imm32 = imm5 << 2;
+        const auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
+        const auto data = ir.ReadMemory32(address);
+
         ir.SetRegister(t, data);
         return true;
     }
 
+    // STRB <Rt>, [<Rn>, #<imm>]
+    // Rt cannot encode R15.
     bool thumb16_STRB_imm(Imm5 imm5, Reg n, Reg t) {
-        u32 imm32 = imm5;
-        // STRB <Rt>, [<Rn>, #<imm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
-        auto data = ir.LeastSignificantByte(ir.GetRegister(t));
+        const u32 imm32 = imm5;
+        const auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
+        const auto data = ir.LeastSignificantByte(ir.GetRegister(t));
+
         ir.WriteMemory8(address, data);
         return true;
     }
 
+    // LDRB <Rt>, [<Rn>, #<imm>]
+    // Rt cannot encode R15.
     bool thumb16_LDRB_imm(Imm5 imm5, Reg n, Reg t) {
-        u32 imm32 = imm5;
-        // LDRB <Rt>, [<Rn>, #<imm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
-        auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
+        const u32 imm32 = imm5;
+        const auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
+        const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
+
         ir.SetRegister(t, data);
         return true;
     }
 
+    // STRH <Rt>, [<Rn>, #<imm5>]
     bool thumb16_STRH_imm(Imm5 imm5, Reg n, Reg t) {
-        u32 imm32 = imm5 << 1;
-        // STRH <Rt>, [<Rn>, #<imm5>]
-        auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
-        auto data = ir.LeastSignificantHalf(ir.GetRegister(t));
+        const u32 imm32 = imm5 << 1;
+        const auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
+        const auto data = ir.LeastSignificantHalf(ir.GetRegister(t));
+
         ir.WriteMemory16(address, data);
         return true;
     }
 
+    // LDRH <Rt>, [<Rn>, #<imm5>]
     bool thumb16_LDRH_imm(Imm5 imm5, Reg n, Reg t) {
-        u32 imm32 = imm5 << 1;
-        // LDRH <Rt>, [<Rn>, #<imm5>]
-        auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
-        auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(address));
+        const u32 imm32 = imm5 << 1;
+        const auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
+        const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(address));
+
         ir.SetRegister(t, data);
         return true;
     }
 
+    // STR <Rt>, [<Rn>, #<imm>]
+    // Rt cannot encode R15.
     bool thumb16_STR_imm_t2(Reg t, Imm5 imm5) {
-        u32 imm32 = imm5 << 2;
-        Reg n = Reg::SP;
-        // STR <Rt>, [<Rn>, #<imm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
-        auto data = ir.GetRegister(t);
+        const u32 imm32 = imm5 << 2;
+        const Reg n = Reg::SP;
+        const auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
+        const auto data = ir.GetRegister(t);
+
         ir.WriteMemory32(address, data);
         return true;
     }
 
+    // LDR <Rt>, [<Rn>, #<imm>]
+    // Rt cannot encode R15.
     bool thumb16_LDR_imm_t2(Reg t, Imm5 imm5) {
-        u32 imm32 = imm5 << 2;
-        Reg n = Reg::SP;
-        // LDR <Rt>, [<Rn>, #<imm>]
-        // Rt cannot encode R15.
-        auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
-        auto data = ir.ReadMemory32(address);
+        const u32 imm32 = imm5 << 2;
+        const Reg n = Reg::SP;
+        const auto address = ir.Add(ir.GetRegister(n), ir.Imm32(imm32));
+        const auto data = ir.ReadMemory32(address);
+
         ir.SetRegister(t, data);
         return true;
     }
 
+    // ADR <Rd>, <label>
+    // Rd cannot encode R15.
     bool thumb16_ADR(Reg d, Imm8 imm8) {
-        u32 imm32 = imm8 << 2;
-        // ADR <Rd>, <label>
-        // Rd cannot encode R15.
-        auto result = ir.Imm32(ir.AlignPC(4) + imm32);
+        const u32 imm32 = imm8 << 2;
+        const auto result = ir.Imm32(ir.AlignPC(4) + imm32);
+
         ir.SetRegister(d, result);
         return true;
     }
 
+    // ADD <Rd>, SP, #<imm>
     bool thumb16_ADD_sp_t1(Reg d, Imm8 imm8) {
-        u32 imm32 = imm8 << 2;
-        // ADD <Rd>, SP, #<imm>
-        auto result = ir.AddWithCarry(ir.GetRegister(Reg::SP), ir.Imm32(imm32), ir.Imm1(0));
+        const u32 imm32 = imm8 << 2;
+        const auto result = ir.AddWithCarry(ir.GetRegister(Reg::SP), ir.Imm32(imm32), ir.Imm1(0));
+
         ir.SetRegister(d, result.result);
         return true;
     }
 
+    // ADD SP, SP, #<imm>
     bool thumb16_ADD_sp_t2(Imm7 imm7) {
-        u32 imm32 = imm7 << 2;
-        Reg d = Reg::SP;
-        // ADD SP, SP, #<imm>
-        auto result = ir.AddWithCarry(ir.GetRegister(Reg::SP), ir.Imm32(imm32), ir.Imm1(0));
+        const u32 imm32 = imm7 << 2;
+        const Reg d = Reg::SP;
+        const auto result = ir.AddWithCarry(ir.GetRegister(Reg::SP), ir.Imm32(imm32), ir.Imm1(0));
+
         ir.SetRegister(d, result.result);
         return true;
     }
 
+    // SUB SP, SP, #<imm>
     bool thumb16_SUB_sp(Imm7 imm7) {
-        u32 imm32 = imm7 << 2;
-        Reg d = Reg::SP;
-        // SUB SP, SP, #<imm>
-        auto result = ir.SubWithCarry(ir.GetRegister(Reg::SP), ir.Imm32(imm32), ir.Imm1(1));
+        const u32 imm32 = imm7 << 2;
+        const Reg d = Reg::SP;
+        const auto result = ir.SubWithCarry(ir.GetRegister(Reg::SP), ir.Imm32(imm32), ir.Imm1(1));
+
         ir.SetRegister(d, result.result);
         return true;
     }
 
+    // SXTH <Rd>, <Rm>
+    // Rd cannot encode R15.
     bool thumb16_SXTH(Reg m, Reg d) {
-        // SXTH <Rd>, <Rm>
-        // Rd cannot encode R15.
-        auto half = ir.LeastSignificantHalf(ir.GetRegister(m));
+        const auto half = ir.LeastSignificantHalf(ir.GetRegister(m));
         ir.SetRegister(d, ir.SignExtendHalfToWord(half));
         return true;
     }
 
+    // SXTB <Rd>, <Rm>
+    // Rd cannot encode R15.
     bool thumb16_SXTB(Reg m, Reg d) {
-        // SXTB <Rd>, <Rm>
-        // Rd cannot encode R15.
-        auto byte = ir.LeastSignificantByte(ir.GetRegister(m));
+        const auto byte = ir.LeastSignificantByte(ir.GetRegister(m));
         ir.SetRegister(d, ir.SignExtendByteToWord(byte));
         return true;
     }
 
+    // UXTH <Rd>, <Rm>
+    // Rd cannot encode R15.
     bool thumb16_UXTH(Reg m, Reg d) {
-        // UXTH <Rd>, <Rm>
-        // Rd cannot encode R15.
-        auto half = ir.LeastSignificantHalf(ir.GetRegister(m));
+        const auto half = ir.LeastSignificantHalf(ir.GetRegister(m));
         ir.SetRegister(d, ir.ZeroExtendHalfToWord(half));
         return true;
     }
 
+    // UXTB <Rd>, <Rm>
+    // Rd cannot encode R15.
     bool thumb16_UXTB(Reg m, Reg d) {
-        // UXTB <Rd>, <Rm>
-        // Rd cannot encode R15.
-        auto byte = ir.LeastSignificantByte(ir.GetRegister(m));
+        const auto byte = ir.LeastSignificantByte(ir.GetRegister(m));
         ir.SetRegister(d, ir.ZeroExtendByteToWord(byte));
         return true;
     }
 
+    // PUSH <reg_list>
+    // reg_list cannot encode for R15.
     bool thumb16_PUSH(bool M, RegList reg_list) {
-        if (M) reg_list |= 1 << 14;
+        if (M) {
+            reg_list |= 1 << 14;
+        }
         if (Common::BitCount(reg_list) < 1) {
             return UnpredictableInstruction();
         }
-        // PUSH <reg_list>
-        // reg_list cannot encode for R15.
+
         const u32 num_bytes_to_push = static_cast<u32>(4 * Common::BitCount(reg_list));
         const auto final_address = ir.Sub(ir.GetRegister(Reg::SP), ir.Imm32(num_bytes_to_push));
         auto address = final_address;
         for (size_t i = 0; i < 16; i++) {
             if (Common::Bit(i, reg_list)) {
                 // TODO: Deal with alignment
-                auto Ri = ir.GetRegister(static_cast<Reg>(i));
+                const auto Ri = ir.GetRegister(static_cast<Reg>(i));
                 ir.WriteMemory32(address, Ri);
                 address = ir.Add(address, ir.Imm32(4));
             }
         }
+
         ir.SetRegister(Reg::SP, final_address);
         // TODO(optimization): Possible location for an RSB push.
         return true;
     }
 
+    // POP <reg_list>
     bool thumb16_POP(bool P, RegList reg_list) {
-        if (P) reg_list |= 1 << 15;
+        if (P) {
+            reg_list |= 1 << 15;
+        }
         if (Common::BitCount(reg_list) < 1) {
             return UnpredictableInstruction();
         }
-        // POP <reg_list>
+
         auto address = ir.GetRegister(Reg::SP);
         for (size_t i = 0; i < 15; i++) {
             if (Common::Bit(i, reg_list)) {
                 // TODO: Deal with alignment
-                auto data = ir.ReadMemory32(address);
+                const auto data = ir.ReadMemory32(address);
                 ir.SetRegister(static_cast<Reg>(i), data);
                 address = ir.Add(address, ir.Imm32(4));
             }
         }
+
         if (Common::Bit<15>(reg_list)) {
             // TODO(optimization): Possible location for an RSB pop.
-            auto data = ir.ReadMemory32(address);
+            const auto data = ir.ReadMemory32(address);
             ir.LoadWritePC(data);
             address = ir.Add(address, ir.Imm32(4));
             ir.SetRegister(Reg::SP, address);
@@ -689,76 +756,81 @@ struct ThumbTranslatorVisitor final {
         }
     }
 
+    // SETEND <endianness>
     bool thumb16_SETEND(bool E) {
-        // SETEND <endianness>
         if (E == ir.current_location.EFlag()) {
             return true;
         }
+
         ir.SetTerm(IR::Term::LinkBlock{ir.current_location.AdvancePC(2).SetEFlag(E)});
         return false;
     }
 
+    // CPS{IE,ID} <a,i,f>
+    // A CPS is treated as a NOP in User mode.
     bool thumb16_CPS(bool, bool, bool, bool) {
-        // CPS{IE,ID} <a,i,f>
-        // A CPS is treated as a NOP in User mode.
         return true;
     }
 
+    // REV <Rd>, <Rm>
+    // Rd cannot encode R15.
     bool thumb16_REV(Reg m, Reg d) {
-        // REV <Rd>, <Rm>
-        // Rd cannot encode R15.
         ir.SetRegister(d, ir.ByteReverseWord(ir.GetRegister(m)));
         return true;
     }
 
+    // REV16 <Rd>, <Rm>
+    // Rd cannot encode R15.
+    // TODO: Consider optimizing
     bool thumb16_REV16(Reg m, Reg d) {
-        // REV16 <Rd>, <Rm>
-        // Rd cannot encode R15.
-        // TODO: Consider optimizing
-        auto Rm = ir.GetRegister(m);
-        auto upper_half = ir.LeastSignificantHalf(ir.LogicalShiftRight(Rm, ir.Imm8(16), ir.Imm1(0)).result);
-        auto lower_half = ir.LeastSignificantHalf(Rm);
-        auto rev_upper_half = ir.ZeroExtendHalfToWord(ir.ByteReverseHalf(upper_half));
-        auto rev_lower_half = ir.ZeroExtendHalfToWord(ir.ByteReverseHalf(lower_half));
-        auto result = ir.Or(ir.LogicalShiftLeft(rev_upper_half, ir.Imm8(16), ir.Imm1(0)).result,
-                            rev_lower_half);
+        const auto Rm = ir.GetRegister(m);
+        const auto upper_half = ir.LeastSignificantHalf(ir.LogicalShiftRight(Rm, ir.Imm8(16), ir.Imm1(0)).result);
+        const auto lower_half = ir.LeastSignificantHalf(Rm);
+        const auto rev_upper_half = ir.ZeroExtendHalfToWord(ir.ByteReverseHalf(upper_half));
+        const auto rev_lower_half = ir.ZeroExtendHalfToWord(ir.ByteReverseHalf(lower_half));
+        const auto result = ir.Or(ir.LogicalShiftLeft(rev_upper_half, ir.Imm8(16), ir.Imm1(0)).result,
+                                  rev_lower_half);
+
         ir.SetRegister(d, result);
         return true;
     }
 
+    // REVSH <Rd>, <Rm>
+    // Rd cannot encode R15.
     bool thumb16_REVSH(Reg m, Reg d) {
-        // REVSH <Rd>, <Rm>
-        // Rd cannot encode R15.
-        auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(ir.GetRegister(m)));
+        const auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(ir.GetRegister(m)));
         ir.SetRegister(d, ir.SignExtendHalfToWord(rev_half));
         return true;
     }
 
+    // STM <Rn>!, <reg_list>
     bool thumb16_STMIA(Reg n, RegList reg_list) {
-        // STM <Rn>!, <reg_list>
         auto address = ir.GetRegister(n);
         for (size_t i = 0; i < 8; i++) {
             if (Common::Bit(i, reg_list)) {
-                auto Ri = ir.GetRegister(static_cast<Reg>(i));
+                const auto Ri = ir.GetRegister(static_cast<Reg>(i));
                 ir.WriteMemory32(address, Ri);
                 address = ir.Add(address, ir.Imm32(4));
             }
         }
+
         ir.SetRegister(n, address);
         return true;
     }
 
+    // STM <Rn>!, <reg_list>
     bool thumb16_LDMIA(Reg n, RegList reg_list) {
-        bool write_back = !Dynarmic::Common::Bit(static_cast<size_t>(n), reg_list);
-        // STM <Rn>!, <reg_list>
+        const bool write_back = !Common::Bit(static_cast<size_t>(n), reg_list);
         auto address = ir.GetRegister(n);
+
         for (size_t i = 0; i < 8; i++) {
             if (Common::Bit(i, reg_list)) {
-                auto data = ir.ReadMemory32(address);
+                const auto data = ir.ReadMemory32(address);
                 ir.SetRegister(static_cast<Reg>(i), data);
                 address = ir.Add(address, ir.Imm32(4));
             }
         }
+
         if (write_back) {
             ir.SetRegister(n, address);
         }
@@ -769,8 +841,8 @@ struct ThumbTranslatorVisitor final {
         return InterpretThisInstruction();
     }
 
+    // BX <Rm>
     bool thumb16_BX(Reg m) {
-        // BX <Rm>
         ir.BXWritePC(ir.GetRegister(m));
         if (m == Reg::R14)
             ir.SetTerm(IR::Term::PopRSBHint{});
@@ -779,8 +851,8 @@ struct ThumbTranslatorVisitor final {
         return false;
     }
 
+    // BLX <Rm>
     bool thumb16_BLX_reg(Reg m) {
-        // BLX <Rm>
         ir.PushRSB(ir.current_location.AdvancePC(2));
         ir.BXWritePC(ir.GetRegister(m));
         ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 2) | 1));
@@ -788,9 +860,9 @@ struct ThumbTranslatorVisitor final {
         return false;
     }
 
+    // SVC #<imm8>
     bool thumb16_SVC(Imm8 imm8) {
-        u32 imm32 = imm8;
-        // SVC #<imm8>
+        const u32 imm32 = imm8;
         ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 2));
         ir.PushRSB(ir.current_location.AdvancePC(2));
         ir.CallSupervisor(ir.Imm32(imm32));
@@ -798,47 +870,53 @@ struct ThumbTranslatorVisitor final {
         return false;
     }
 
+    // B<cond> <label>
     bool thumb16_B_t1(Cond cond, Imm8 imm8) {
-        s32 imm32 = Common::SignExtend<9, s32>(imm8 << 1) + 4;
         if (cond == Cond::AL) {
             return thumb16_UDF();
         }
-        // B<cond> <label>
-        auto then_location = ir.current_location.AdvancePC(imm32);
-        auto else_location = ir.current_location.AdvancePC(2);
+
+        const s32 imm32 = Common::SignExtend<9, s32>(imm8 << 1) + 4;
+        const auto then_location = ir.current_location.AdvancePC(imm32);
+        const auto else_location = ir.current_location.AdvancePC(2);
+
         ir.SetTerm(IR::Term::If{cond, IR::Term::LinkBlock{then_location}, IR::Term::LinkBlock{else_location}});
         return false;
     }
 
+    // B <label>
     bool thumb16_B_t2(Imm11 imm11) {
-        s32 imm32 = Common::SignExtend<12, s32>(imm11 << 1) + 4;
-        // B <label>
-        auto next_location = ir.current_location.AdvancePC(imm32);
+        const s32 imm32 = Common::SignExtend<12, s32>(imm11 << 1) + 4;
+        const auto next_location = ir.current_location.AdvancePC(imm32);
+
         ir.SetTerm(IR::Term::LinkBlock{next_location});
         return false;
     }
 
+    // BL <label>
     bool thumb32_BL_imm(Imm11 hi, Imm11 lo) {
-        s32 imm32 = Common::SignExtend<23, s32>((hi << 12) | (lo << 1)) + 4;
-        // BL <label>
         ir.PushRSB(ir.current_location.AdvancePC(4));
         ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1));
-        auto new_location = ir.current_location.AdvancePC(imm32);
+
+        const s32 imm32 = Common::SignExtend<23, s32>((hi << 12) | (lo << 1)) + 4;
+        const auto new_location = ir.current_location.AdvancePC(imm32);
         ir.SetTerm(IR::Term::LinkBlock{new_location});
         return false;
     }
 
+    // BLX <label>
     bool thumb32_BLX_imm(Imm11 hi, Imm11 lo) {
-        s32 imm32 = Common::SignExtend<23, s32>((hi << 12) | (lo << 1));
         if ((lo & 1) != 0) {
             return UnpredictableInstruction();
         }
-        // BLX <label>
+
         ir.PushRSB(ir.current_location.AdvancePC(4));
         ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1));
-        auto new_location = ir.current_location
-                              .SetPC(ir.AlignPC(4) + imm32)
-                              .SetTFlag(false);
+
+        const s32 imm32 = Common::SignExtend<23, s32>((hi << 12) | (lo << 1));
+        const auto new_location = ir.current_location
+                                    .SetPC(ir.AlignPC(4) + imm32)
+                                    .SetTFlag(false);
         ir.SetTerm(IR::Term::LinkBlock{new_location});
         return false;
     }
@@ -858,8 +936,9 @@ bool IsThumb16(u16 first_part) {
 
 std::tuple<u32, ThumbInstSize> ReadThumbInstruction(u32 arm_pc, MemoryReadCodeFuncType memory_read_code) {
     u32 first_part = memory_read_code(arm_pc & 0xFFFFFFFC);
-    if ((arm_pc & 0x2) != 0)
+    if ((arm_pc & 0x2) != 0) {
         first_part >>= 16;
+    }
     first_part &= 0xFFFF;
 
     if (IsThumb16(static_cast<u16>(first_part))) {
@@ -871,8 +950,9 @@ std::tuple<u32, ThumbInstSize> ReadThumbInstruction(u32 arm_pc, MemoryReadCodeFu
     // These always start with 0b11101, 0b11110 or 0b11111.
 
     u32 second_part = memory_read_code((arm_pc + 2) & 0xFFFFFFFC);
-    if (((arm_pc + 2) & 0x2) != 0)
+    if (((arm_pc + 2) & 0x2) != 0) {
         second_part >>= 16;
+    }
     second_part &= 0xFFFF;
 
     return std::make_tuple(static_cast<u32>((first_part << 16) | second_part), ThumbInstSize::Thumb32);