From fe15cbd50ede6190004c065e51805b4757c079c9 Mon Sep 17 00:00:00 2001
From: MerryMage <MerryMage@users.noreply.github.com>
Date: Fri, 19 Aug 2016 00:40:18 +0100
Subject: [PATCH] translate_arm/parallel: Detect UNPREDICTABLE instructions

---
 src/frontend/translate/translate_arm/parallel.cpp | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/frontend/translate/translate_arm/parallel.cpp b/src/frontend/translate/translate_arm/parallel.cpp
index c32ee592..8dffd567 100644
--- a/src/frontend/translate/translate_arm/parallel.cpp
+++ b/src/frontend/translate/translate_arm/parallel.cpp
@@ -61,6 +61,8 @@ bool ArmTranslatorVisitor::arm_USUB16(Cond cond, Reg n, Reg d, Reg m) {
 
 // Parallel Add/Subtract (Saturating) instructions
 bool ArmTranslatorVisitor::arm_QADD8(Cond cond, Reg n, Reg d, Reg m) {
+    if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
+        return UnpredictableInstruction();
     if (ConditionPassed(cond)) {
         auto result = ir.PackedSaturatedAddS8(ir.GetRegister(n), ir.GetRegister(m));
         ir.SetRegister(d, result);
@@ -69,6 +71,8 @@ bool ArmTranslatorVisitor::arm_QADD8(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_QADD16(Cond cond, Reg n, Reg d, Reg m) {
+    if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
+        return UnpredictableInstruction();
     if (ConditionPassed(cond)) {
         auto result = ir.PackedSaturatedAddS16(ir.GetRegister(n), ir.GetRegister(m));
         ir.SetRegister(d, result);
@@ -85,6 +89,8 @@ bool ArmTranslatorVisitor::arm_QSAX(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_QSUB8(Cond cond, Reg n, Reg d, Reg m) {
+    if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
+        return UnpredictableInstruction();
     if (ConditionPassed(cond)) {
         auto result = ir.PackedSaturatedSubS8(ir.GetRegister(n), ir.GetRegister(m));
         ir.SetRegister(d, result);
@@ -93,6 +99,8 @@ bool ArmTranslatorVisitor::arm_QSUB8(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_QSUB16(Cond cond, Reg n, Reg d, Reg m) {
+    if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
+        return UnpredictableInstruction();
     if (ConditionPassed(cond)) {
         auto result = ir.PackedSaturatedSubS16(ir.GetRegister(n), ir.GetRegister(m));
         ir.SetRegister(d, result);
@@ -125,6 +133,8 @@ bool ArmTranslatorVisitor::arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) {
+    if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
+        return UnpredictableInstruction();
     if (ConditionPassed(cond)) {
         auto result = ir.PackedSaturatedSubU8(ir.GetRegister(n), ir.GetRegister(m));
         ir.SetRegister(d, result);
@@ -133,6 +143,8 @@ bool ArmTranslatorVisitor::arm_UQSUB8(Cond cond, Reg n, Reg d, Reg m) {
 }
 
 bool ArmTranslatorVisitor::arm_UQSUB16(Cond cond, Reg n, Reg d, Reg m) {
+    if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
+        return UnpredictableInstruction();
     if (ConditionPassed(cond)) {
         auto result = ir.PackedSaturatedSubU16(ir.GetRegister(n), ir.GetRegister(m));
         ir.SetRegister(d, result);