diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index fceda5a0..c21dbfe2 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -288,7 +288,7 @@ INST(RORV,                   "RORV",                                      "z0011
 //INST(RBIT_int,               "RBIT",                                      "z101101011000000000000nnnnnddddd")
 INST(REV16_int,              "REV16",                                     "z101101011000000000001nnnnnddddd")
 INST(REV,                    "REV",                                       "z10110101100000000001onnnnnddddd")
-//INST(CLZ_int,                "CLZ",                                       "z101101011000000000100nnnnnddddd")
+INST(CLZ_int,                "CLZ",                                       "z101101011000000000100nnnnnddddd")
 //INST(CLS_int,                "CLS",                                       "z101101011000000000101nnnnnddddd")
 INST(REV32_int,              "REV32",                                     "1101101011000000000010nnnnnddddd")
 //INST(PACDA,                  "PACDA, PACDZA",                             "110110101100000100Z010nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/data_processing_register.cpp b/src/frontend/A64/translate/impl/data_processing_register.cpp
index 01afeabf..f775cd8d 100644
--- a/src/frontend/A64/translate/impl/data_processing_register.cpp
+++ b/src/frontend/A64/translate/impl/data_processing_register.cpp
@@ -9,6 +9,16 @@
 namespace Dynarmic {
 namespace A64 {
 
+bool TranslatorVisitor::CLZ_int(bool sf, Reg Rn, Reg Rd) {
+    const size_t datasize = sf ? 64 : 32;
+
+    const IR::U32U64 operand = X(datasize, Rn);
+    const IR::U32U64 result = ir.CountLeadingZeros(operand);
+
+    X(datasize, Rd, result);
+    return true;
+}
+
 bool TranslatorVisitor::REV(bool sf, bool opc_0, Reg Rn, Reg Rd) {
     const size_t datasize = sf ? 64 : 32;