Citra-emu/dynarmic-android
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Author SHA1 Message Date
SachinVin
5c9179e2db backend/a64: Port reg_alloc 2020-05-23 19:54:36 +05:30
SachinVin
a37f9c4cc6 backend/a64: Port ABI functions 2020-05-23 19:54:36 +05:30
SachinVin
ab07872025 backend/a64: Port perfmap 2020-05-23 19:54:36 +05:30
SachinVin
be80e558c9 backend/a64: Port hostloc 2020-05-23 19:54:36 +05:30
SachinVin
9ca0155c19 backend/a64: Devirtualize functions for a64 2020-05-23 19:54:35 +05:30
SachinVin
fbb03a2a1b backend/a64: Port block_range_info 2020-05-23 19:54:35 +05:30
SachinVin
19b7fba235 CMakeModules\DetectArchitecture.cmake: Refactor ARCHITECTURE to DYNARMIC_ARCHITECTURE 
Don't rely on super-project's definition of ARCHITECTURE
 2020-05-23 19:54:35 +05:30
SachinVin
9bcbdacd2b [HACK] A32/exception_generating: Interpret undefined instructions 2020-05-23 19:54:35 +05:30
SachinVin
c72550f7d9 [HACK] CMakeLists: Do not build A64 tests on AArch64 2020-05-23 19:54:34 +05:30
MerryMage
8fdeb84822 fuzz_thumb: Add [JitA64] tag to supported instructions 2020-05-23 19:54:34 +05:30
SachinVin
4e4f2b8ef0 backend/A64: Port a32_jitstate 2020-05-23 19:54:34 +05:30
MerryMage
8de86b391f code_block: Support Windows and fix munmap check 2020-05-23 19:54:33 +05:30
SachinVin
0a55e1b11e ir_opt: Port a32_merge_interpreter_blocks 2020-05-23 19:54:33 +05:30
SachinVin
f654dbb29b assert: Use __android_log_print on Android 2020-05-23 19:54:33 +05:30
SachinVin
668d20391a CMakeLists: xbyak should only be linked on x64 2020-05-23 19:54:32 +05:30
SachinVin
0ce4fa4480 a64_emitter: Fix ABI push and pop 2020-05-23 19:54:32 +05:30
SachinVin
ddc8b7f932 a64_emitter: More style cleanup 2020-05-23 19:54:32 +05:30
SachinVin
6010c48bd0 a64_emitter: Style cleanup 2020-05-23 19:54:31 +05:30
BreadFish64
b8369d77ac Backend/A64: add jitstate_info.h 2020-05-23 19:54:31 +05:30
BreadFish64
7905eeb94b Backend/A64: Add Dolphin's ARM emitter 2020-05-23 19:54:31 +05:30
BreadFish64
f7664d9161 Add aarch64 CI 2020-05-23 19:54:31 +05:30
Lioncash
659d78c9c4 A32: Implement ASIMD VSWP 
A trivial one to implement, this just swaps the contents of two
registers in place.
 2020-05-22 19:43:24 +01:00
MerryMage
d0d50c4824 print_info: Use VFP and ASIMD decoders to get dynarmic name for instruction 2020-05-17 22:48:14 +01:00
MerryMage
d0075f4ea6 print_info: Use LLVM to disassemble A32 2020-05-17 22:30:46 +01:00
MerryMage
c59a127e86 opcodes: Switch from std::map to std::array 
Optimization.
 2020-05-17 17:01:39 +01:00
MerryMage
d0b45f6150 A32: Implement ARMv8 VST{1-4} (multiple) 2020-05-17 17:01:39 +01:00
Lioncash
eb332b3836 asimd_three_same: Unify BitwiseInstructionWithDst with BitwiseInstruction 
Now that all bitwise instructions are implemented, we can unify all of
them together using if constexpr.
 2020-05-16 20:22:12 +01:00
Lioncash
f42b3ad4a0 A32: Implement ASIMD VBIF (register) 2020-05-16 20:22:12 +01:00
Lioncash
ee9a81dcba A32: Implement ASIMD VBIT (register) 2020-05-16 20:22:12 +01:00
Lioncash
d624059ead A32: Implement ASIMD VBSL (register) 2020-05-16 20:22:12 +01:00
Lioncash
66663cf8e7 asimd_three_same: Collapse all bitwise implementations into a single code path 
Less code and results in only writing the parts that matter once.
 2020-05-16 20:22:12 +01:00
Lioncash
4b5e3437cf A32: Implement ASIMD VEOR (register) 2020-05-16 20:22:12 +01:00
Lioncash
67b284f6fa A32: Implement ASIMD VORN (register) 2020-05-16 20:22:12 +01:00
Lioncash
1fdd90ca2a A32: Implement ASIMD VORR (register) 2020-05-16 20:22:12 +01:00
Lioncash
9b93a9de46 a32_jitstate: Remove obsoleted debug assert 2020-05-16 20:22:12 +01:00
Lioncash
64fa804dd4 A32: Implement ASIMD VBIC (register) 2020-05-16 20:22:12 +01:00
Lioncash
0441ab81a1 A32: Implement ASIMD VAND (register) 2020-05-16 20:22:12 +01:00
Lioncash
1b25e867ae asimd_load_store_structures: Simplify ToExtRegD() 
ExtReg has a supplied operator+, so we can make use of that instead.
 2020-05-16 11:27:22 -04:00
MerryMage
2169653c50 a64_emit_x64: Invalid regalloc code for EmitA64ExclusiveReadMemory128 
Attempted to allocate args[0] after end of allocation scope
 2020-05-16 14:11:23 +01:00
MerryMage
1a0bc5ba91 A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple) 2020-05-16 14:11:23 +01:00
MerryMage
e7f1a0d408 A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H} 2020-05-15 21:07:36 +01:00
Lioncash
8808b8c479 cpu_info: Make test non-allocating 
Same behavior, but makes it non-allocating by using a constexpr
std::array instead of a std::vector.
 2020-05-12 09:52:55 +01:00
Lioncash
af3b65b135 decoder_detail: Mark GetMaskAndExpect() as constexpr 
Elides quite a bit of code at runtime when constructing the decoding
tables.
 2020-05-11 08:29:06 +01:00
MerryMage
59db2c191a VFPv3: Implement VMOV (immediate) 2020-05-10 15:09:37 +01:00
MerryMage
7f77a04900 fuzz_arm: Do not test vfp_VMRS 
This may emit a vmrs *, fpscr instruction.
This results in fuzz failures due to slight inaccuracies in fpscr emulation.
 2020-05-10 14:47:21 +01:00
MerryMage
3c86d58064 VFPv4: Implement VCVTB, VCVTT 2020-05-10 14:45:18 +01:00
MerryMage
010fab9a0e VFPv4: Implement VFMA, VFMS 2020-05-10 14:20:11 +01:00
MerryMage
8e97b10acb VFPv4: Implement VFNMS, VFNMA 2020-05-10 14:14:03 +01:00
MerryMage
6df660c889 fuzz_arm: Ensure all instructions are fuzzed 
* VFP instructions were not getting fuzzed due to matching coprocessor instructions (as invalid instructions)
* Fix VPOP writeback for doubles when (imm8 & 1) == 1
* Do not accidentally fuzz unimplemented unconditional instructions
 2020-05-10 13:57:39 +01:00
MerryMage
9a38c7324f A32: Add decoders for remaining v7 instructions 2020-05-10 10:50:34 +01:00