Citra-emu/dynarmic-android
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201 Commits

Author SHA1 Message Date
Lioncash
ccf9493653 A64: Implement AESD 2018-02-03 23:11:46 +00:00
Lioncash
33bc59c55a A64: Implement AESE 2018-02-03 23:11:46 +00:00
MerryMage
a7209dc2f7 IR: Add IR instruction NZCVFromPackedFlags 
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
 2018-02-03 13:41:36 +00:00
MerryMage
2fd70e56ce A64: Implement FMOV (scalar, immediate) 2018-02-03 00:52:48 +00:00
MerryMage
fcabd95ad0 IR: Merge U32 and U64 variants of FP instructions 2018-02-02 21:55:23 +00:00
MerryMage
cc40b83ed0 IR: Implement VectorSetElement{8,16,32,64} 2018-02-02 21:00:12 +00:00
Lioncash
b608979be9 A64: Implement AESIMC and AESMC 2018-02-02 17:35:16 +00:00
Lioncash
7fb386aa1c A64: Implement CRC32 2018-01-29 17:06:17 +00:00
Lioncash
0216cbd2a5 A64: Implement CRC32C 2018-01-28 12:20:56 +00:00
MerryMage
39b7625e9d ir_emitter: Allow the insertion point for new instructions to be set 2018-01-27 00:38:43 +00:00
Lioncash
dbddb4858a A64: Implement EXTR 2018-01-26 22:07:48 +00:00
Lioncash
8c013e7928 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2018-01-26 17:06:48 +00:00
MerryMage
f7e8a2259a IR: Implement IR instructions VectorEqual{8,16,32,64,128} 2018-01-26 01:52:06 +00:00
Fernando Sahmkow
5ffd11d140 A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142) 2018-01-26 00:57:56 +00:00
MerryMage
314e020992 IR: Add IR instruction VectorZeroUpper 2018-01-24 17:11:13 +00:00
FernandoS27
d1664096f5 Implemented SDIV and UDIV instructions 2018-01-24 17:09:00 +00:00
MerryMage
5421c90216 IR: Add IR instruction VectorGetElement{8,16,32,64} 2018-01-24 16:18:58 +00:00
MerryMage
3932d6d695 IR: Add IR instruction ZeroExtendToQuad 2018-01-24 16:18:58 +00:00
MerryMage
6f1c44e311 IR: Implement Vector{Lower,}Broadcast{8,16,32,64} 2018-01-24 12:01:26 +00:00
MerryMage
ae603909d6 ir_emitted: Remove unimplemented IR instruction Unimplemented 2018-01-23 22:16:15 +00:00
MerryMage
dfcbe5bd2f IR: Implement Vector{Lower,}PairedAdd{8,16,32,64} 2018-01-23 17:46:28 +00:00
Lioncash
768e5bcf9c A64: Implement MADD and MSUB 2018-01-23 16:08:05 +00:00
Lioncash
585e77d20e opcodes: Add 64-bit CountLeadingZeroes opcode 2018-01-23 11:55:09 +00:00
MerryMage
f2dc9c7727 data_processing_register: Clean-up 2018-01-22 22:47:01 +00:00
MerryMage
a6d17e6bb0 A64: Implement AND (vector) 2018-01-21 18:27:06 +00:00
MerryMage
d333b5dcee A64: Implement ADD (vector, vector) 2018-01-21 17:56:27 +00:00
MerryMage
9fc1570788 IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
 2018-01-19 01:09:46 +00:00
MerryMage
2f84137f5b IR: Implement Conditional Select 2018-01-18 11:36:52 +00:00
MerryMage
305456b407 A64: Implement compare and branch 2018-01-09 18:57:06 +00:00
MerryMage
f3e763a667 A64: Implement logical 2018-01-09 18:57:06 +00:00
MerryMage
8a8dcad250 A64: Implement addsub instructions 2018-01-09 18:57:06 +00:00
MerryMage
1431cedcaa A64: Implement ADD_shifted 2018-01-09 18:57:06 +00:00
MerryMage
512dae0361 IR: Compile-time type-checking of IR 2018-01-09 18:20:57 +00:00
MerryMage
42c83fadce IR: Split off A32 specific opcodes 2018-01-09 18:20:57 +00:00
MerryMage
f5402c8d82 A32: Split off A32 specific IREmitter 2018-01-09 18:20:57 +00:00
MerryMage
3e569047a5 Label A32 specific code appropriately 2018-01-09 18:20:57 +00:00
MerryMage
976a098bf6 jit_state: Split off CPSR.NZCV 2017-12-12 14:24:07 +00:00
MerryMage
311b6609aa Implement IR instruction PackedSelect, reimplement SEL 2017-11-25 16:33:48 +00:00
MerryMage
c421a137c0 VCMP and VCMPE were the other way around 
- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
 2017-11-22 17:45:37 +00:00
MerryMage
05e97058c3 parallel: Add and Subtract with Exchange improvements 
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
 2017-03-24 15:56:24 +00:00
MerryMage
48693eb6ff Implement coprocessor-related microinstructions 
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
 2017-01-08 14:56:06 +00:00
MerryMage
1efd3a764d IR: Remove unused microinstructions NegateLowWord and NegateHighWord 2017-01-05 20:16:39 +00:00
FernandoS27
d5610eb26c Implement UHASX, UHSAX, SHASX and SHSAX (#75) 2016-12-28 21:32:22 +00:00
Fernando Sahmkow
677f62dd6f Implement SHSUB8 and SHSUB16 (#74) 
* Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
 2016-12-22 12:02:24 +00:00
MerryMage
6a269a6ebd IR: Add microinstructions UnsignedSaturation and SignedSaturation 2016-12-21 19:51:25 +00:00
FernandoS27
8919265d2c Implement SADD8, SADD16, SSUB8, SSUB16, USUB16 2016-12-20 21:52:38 +00:00
FernandoS27
3f6ecfe245 Implemented USAD8 and USADA8 2016-12-20 21:52:38 +00:00
MerryMage
96e46ba6b5 Implement QADD, QSUB, QDADD, QDSUB 2016-12-15 22:34:29 +00:00
MerryMage
52e1445f43 Implement USUB8 2016-12-05 00:29:15 +00:00
MerryMage
5c1aab1666 Implement CLZ 
Includes tests
 2016-12-04 22:56:33 +00:00