8 Commits

Author SHA1 Message Date
MerryMage
49f1de3188 Direct Page Table Access: Handle address spaces less than the full 64-bit in size 2018-02-12 21:26:23 +00:00
MerryMage
406725e533 Implement direct page table access 2018-02-12 20:51:03 +00:00
MerryMage
7a161ed35c A64: Partially implement MRS 2018-02-12 00:06:44 +00:00
MerryMage
1ba2642742 Implement DC instructions 2018-02-11 23:12:28 +00:00
MerryMage
d6589fe3ee IR: Add IR instructions A64Memory{Read,Write}128
This implementation only works on macOS and Linux.
2018-01-24 16:18:58 +00:00
MerryMage
ed63cc7ae9 interface: Move Vector typedef to config.h 2018-01-24 16:18:58 +00:00
MerryMage
9ab130490b A64: Add ExceptionRaised IR instruction
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2018-01-13 18:06:06 +00:00
MerryMage
ef6fd92fed A64: Backend framework 2018-01-09 18:57:06 +00:00