Citra-emu/dynarmic-android
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218 Commits

Author SHA1 Message Date
MerryMage
2e14326fd5 assert: Use fmt in ASSERT_MSG 2018-01-28 00:00:58 +00:00
Lioncash
8c013e7928 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2018-01-26 17:06:48 +00:00
Lioncash
cdb588dab5 General: Default constructors and destructors where applicable 2018-01-24 09:07:22 +00:00
MerryMage
f014a5bec7 emit_x64: Extract BlockRangeInformation, remove template parameter 2018-01-23 19:44:35 +00:00
MerryMage
5f5e664a66 emit_x64: Use JitStateInfo 2018-01-23 19:44:35 +00:00
MerryMage
961e64dfaf backend_x64: Split emit_x64 2018-01-23 17:46:28 +00:00
Lioncash
585e77d20e opcodes: Add 64-bit CountLeadingZeroes opcode 2018-01-23 11:55:09 +00:00
MerryMage
a6d17e6bb0 A64: Implement AND (vector) 2018-01-21 18:27:06 +00:00
MerryMage
d333b5dcee A64: Implement ADD (vector, vector) 2018-01-21 17:56:27 +00:00
MerryMage
9fc1570788 IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
 2018-01-19 01:09:46 +00:00
MerryMage
adccbf3c6b reg_alloc: Consider bitwidth of data and registers when emitting instructions 2018-01-18 13:00:16 +00:00
MerryMage
2f84137f5b IR: Implement Conditional Select 2018-01-18 11:36:52 +00:00
MerryMage
1bfa04d7ac emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64 2018-01-13 18:06:06 +00:00
MerryMage
83afe4353c Misc. fixups of MSVC build 2018-01-12 18:13:53 +00:00
MerryMage
c029aef4da emit_x86: Fix nzcv for EmitSub 2018-01-09 18:57:07 +00:00
MerryMage
305456b407 A64: Implement compare and branch 2018-01-09 18:57:06 +00:00
MerryMage
f3e763a667 A64: Implement logical 2018-01-09 18:57:06 +00:00
MerryMage
8a8dcad250 A64: Implement addsub instructions 2018-01-09 18:57:06 +00:00
MerryMage
1431cedcaa A64: Implement ADD_shifted 2018-01-09 18:57:06 +00:00
MerryMage
ef6fd92fed A64: Backend framework 2018-01-09 18:57:06 +00:00
MerryMage
be094ff150 Final A32 refactor 2018-01-09 18:20:57 +00:00
MerryMage
faf64f4a5f EmitX64: JitState type as template parameter 2018-01-09 18:20:57 +00:00
MerryMage
d95a01bcb3 Package up emit context 2018-01-09 18:20:57 +00:00
MerryMage
d67332e333 Rename JitState to A32JitState 2018-01-09 18:20:57 +00:00
MerryMage
053c58f48f backend_x64: Split A32 specific emission into separate class 2018-01-09 18:20:57 +00:00
MerryMage
42c83fadce IR: Split off A32 specific opcodes 2018-01-09 18:20:57 +00:00
MerryMage
f5402c8d82 A32: Split off A32 specific IREmitter 2018-01-09 18:20:57 +00:00
MerryMage
3e569047a5 Label A32 specific code appropriately 2018-01-09 18:20:57 +00:00
Phanto-m
672069608f emit_x64: InvalidateCacheRanges: erase blocks after iterating through the map (#124) 2017-12-18 15:13:40 +00:00
MerryMage
ce9c265df0 EmitPackedHalvingSub{U,S}16: SSE2 implementation 2017-12-14 15:08:18 +00:00
MerryMage
13fa10e743 Merge branch 'misc' 
These commits introduce context save and restore, and a small number of
optimizations that depend on their use for performance.
 2017-12-12 22:07:39 +00:00
MerryMage
a7d2fac2d3 EmitPackedHalvingAddU8: Add SSE2 implementation 2017-12-12 16:11:22 +00:00
MerryMage
16ed4bd511 EmitPackedHalvingAdd{U,S}16: Add SSE2 implementation 2017-12-12 15:57:26 +00:00
MerryMage
afc47e1733 emit_x64: EmitSet{Register,ExtendedRegister32,ExtendedRegister64}: Store from current source 2017-12-12 15:28:37 +00:00
MerryMage
dd07033dce emit_x64: Optimize code emitted by EmitGetCpsr 2017-12-12 14:25:22 +00:00
MerryMage
976a098bf6 jit_state: Split off CPSR.NZCV 2017-12-12 14:24:07 +00:00
MerryMage
cfdc8d882f jit_state: Split off CPSR.Q 2017-12-12 14:23:34 +00:00
MerryMage
2e6eda226c jit_state: Split off CPSR.{E,T} 
This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
 2017-12-12 14:23:34 +00:00
MerryMage
809ca5fcc2 jit_state: Split off CPSR.GE 2017-12-12 14:23:34 +00:00
MerryMage
e1daadff81 jit_state: Hide cpsr implementation 2017-12-12 14:23:34 +00:00
MerryMage
5b23e5b52e emit_x64: Make RSB a stack 2017-12-12 14:23:32 +00:00
MerryMage
2577803203 emit_x64: Arguments to MostSignificantBit and IsZero are 32-bit 2017-12-09 16:26:11 +00:00
MerryMage
a2bd9a0e12 emit_x64: Reduce mxscr operations in EmitGetFpscr and EmitSetFpscr 2017-12-09 16:25:58 +00:00
MerryMage
4110494ac4 emit_x64: Use boost::icl::interval_map to speed up ranged invalidation 2017-12-06 20:55:29 +00:00
MerryMage
b6b061f244 emit_x64: Remove unnecessary ABI overhead in ReadMemory, WriteMemory 2017-12-03 19:46:26 +00:00
MerryMage
f343c56268 block_of_code: Move MXCSR switching out of dispatch loop 
Also clarify MXCSR entry/exit terminology
 2017-12-03 15:39:47 +00:00
MerryMage
024fa2461c Add AddTicks and GetTicksRemaining callbacks 2017-12-03 15:18:08 +00:00
MerryMage
bb87d2540c Remove unnecessary use of boost::make_optional 
Closes #119.
 2017-11-28 20:56:54 +00:00
MerryMage
92ae4c783b emit_x86: Standardize time of DefineValue call 2017-11-27 19:51:54 +00:00
MerryMage
993946fad8 emit_x64: Perform mask creation for packed instructions in SSE 2017-11-25 19:34:30 +00:00