Citra-emu/dynarmic-android
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43 Commits

Author SHA1 Message Date
MerryMage
0fd75fd9cb A64: Implement system registers FPCR and FPSR 2018-02-20 17:38:29 +00:00
MerryMage
22285842af A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR 2018-02-13 12:30:58 +00:00
MerryMage
b733479b5e A64: Implement DSB, DMB 2018-02-11 23:27:28 +00:00
MerryMage
1ba2642742 Implement DC instructions 2018-02-11 23:12:28 +00:00
MerryMage
4df6c424df Forward declare IR::Opcode and IR::Type where possible 2018-02-11 11:52:44 +00:00
Lioncash
cd3113c208 microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement 2018-02-05 00:45:11 +00:00
MerryMage
9232be5553 ir_opt: Add A64 Get/Set Elimination Pass 2018-01-27 00:38:43 +00:00
MerryMage
0c1c82a937 IR: Implement IR instructions A64{Get,Set}S 2018-01-26 18:38:30 +00:00
Lioncash
8c013e7928 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2018-01-26 17:06:48 +00:00
MerryMage
d99c99aabb microinstruction: Missed A64{Read,Write}Memory128 from opcode information 2018-01-25 23:56:14 +00:00
MerryMage
2b59e2ba0b microinstruction: bug: Add missing opcodes 2018-01-23 17:46:28 +00:00
MerryMage
adccbf3c6b reg_alloc: Consider bitwidth of data and registers when emitting instructions 2018-01-18 13:00:16 +00:00
MerryMage
9ab130490b A64: Add ExceptionRaised IR instruction 
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
 2018-01-13 18:06:06 +00:00
MerryMage
16e50ca0db A32: Implement load stores (immediate) 2018-01-10 01:30:30 +00:00
MerryMage
f19f014a42 A64: Implement SVC 2018-01-09 18:57:07 +00:00
MerryMage
305456b407 A64: Implement compare and branch 2018-01-09 18:57:06 +00:00
MerryMage
08c25c9ae7 A64: PSTATE access and tests 2018-01-09 18:57:06 +00:00
MerryMage
c4abd1fda1 A64: Implement branch (register) 2018-01-09 18:57:06 +00:00
MerryMage
f3e763a667 A64: Implement logical 2018-01-09 18:57:06 +00:00
MerryMage
8a8dcad250 A64: Implement addsub instructions 2018-01-09 18:57:06 +00:00
MerryMage
1431cedcaa A64: Implement ADD_shifted 2018-01-09 18:57:06 +00:00
MerryMage
42c83fadce IR: Split off A32 specific opcodes 2018-01-09 18:20:57 +00:00
MerryMage
976a098bf6 jit_state: Split off CPSR.NZCV 2017-12-12 14:24:07 +00:00
MerryMage
67c8e6e695 microinstruction: Remove DecrementRemainingUses 2017-11-27 20:10:23 +00:00
MerryMage
523ae542f4 microinstruction: Implement HasAssociatedPseudoOperation 2017-04-04 13:10:50 +01:00
MerryMage
92a01b0cd8 Prefer ASSERT to DEBUG_ASSERT 2017-02-26 23:30:40 +00:00
MerryMage
bbeea72eba ir_opt: Remove redundant shift instructions 2017-02-26 15:28:14 +00:00
MerryMage
4ed8ee7489 microinstruction: Void arguments when invalidating instruction 2017-02-18 21:29:23 +00:00
MerryMage
5f7ffe0d0b microinstruction: Implement Inst::AreAllArgsImmediates 2017-01-29 22:56:59 +00:00
MerryMage
22804dc6a5 microinstruction: Arguments of Inst::Use and Inst::UndoUse should be const 2017-01-29 22:53:46 +00:00
MerryMage
1d4446cad5 microinstruction: Removed unnecessary reference from argument of Inst::ReplaceUsesWith 2017-01-29 22:52:33 +00:00
MerryMage
48693eb6ff Implement coprocessor-related microinstructions 
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
 2017-01-08 14:56:06 +00:00
MerryMage
7cad6949e7 IR: Implement new pseudo-operation GetGEFromOp 2016-12-04 20:52:06 +00:00
MerryMage
e166965f3e Implement VCMP 2016-12-03 11:41:09 +00:00
Mat M
de1f831d79 microinstruction: Make use_count private (#53) 
Makes the operation a part of the direct interface.
 2016-11-30 21:51:06 +00:00
MerryMage
b6f7b8babd ir: Implement GetGEFlags, SetGEFlags 2016-11-23 19:44:27 +00:00
MerryMage
dca3b2f079 Implement VMRS and VMSR 2016-08-26 22:47:54 +01:00
MerryMage
4322c0907c microinstruction: Rename FindUseWithOpcode to GetAssociatedPseudoOperation, encapsulate associated variables 2016-08-25 21:08:47 +01:00
MerryMage
e0f9dead5d microinstruction: Identity's type depends on the type of its argument 2016-08-23 15:48:30 +01:00
MerryMage
8d1b9f32ca Standardize indentation of switch statments 2016-08-23 12:19:27 +01:00
Lioncash
47f285249b microinstruction: Introduce convenience informational functions 
Whenever more rigorous optimizations are attempted (or even basic ones),
it's usually helpful to know what overall kind of instruction is being
dealt with, in the event certain classes of instructions may be eligible
for optimization.
 2016-08-22 21:36:48 +01:00
MerryMage
192a0029be ir/opcodes: Implement IR::AreTypesCompatible 
Type-checking is now occuring in more than one place.
 2016-08-19 01:34:14 +01:00
Lioncash
841098a0bc ir: separate components out a little more 2016-08-17 20:46:21 +01:00