Merry
0f2f6ef789
Merge pull request #456 from lioncash/mov
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A64: Enable FMOV (general) for half-precision floating point
2019-03-22 22:27:48 +00:00
Lioncash
7627fa389b
A64: Enable FMOV (general) for half-precision floating point
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This just transfers values between vector registers and general-purpose
registers with no conversions performed, so this is trivial to add
support for half-precision to.
2019-03-22 15:18:12 -04:00
Merry
004adfe844
Merge pull request #455 from lioncash/sqrdmulh-scalar
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A64: Implement SQRDMULH and SQDMULL's scalar indexed variants
2019-03-22 12:43:53 +00:00
Lioncash
5c6becc402
A64: Implement SQRDMULH's scalar indexed element variant
2019-03-20 23:26:55 -04:00
Lioncash
2d78390d43
A64: Implement SQDMULL{2}'s scalar indexed element variant
2019-03-20 23:05:07 -04:00
Lioncash
3238864878
simd_scalar_x_indexed_element: Factor out index and Vm argument construction
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This will be useful in the implementations of SQRDMULH and SQDMULL{2} as
well.
2019-03-20 22:28:46 -04:00
Lioncash
996a618643
simd_vector_x_indexed_element: Deduplicate index and Vm operand construction
2019-03-20 16:21:48 -04:00
Lioncash
328211b0c5
A64: Implement SQDMULL{2}'s by-element variant
2019-03-20 15:36:27 -04:00
Lioncash
b4ca6b67d1
A64: Implement SQRDMULH's by-index vector variant
2019-03-20 14:05:41 -04:00
Lioncash
f8ad1819ab
A64: Implement FRECPX's half-precision floating point variant
2019-03-09 20:08:01 -05:00
Lioncash
db67a42244
frontend/ir/ir_emitter: Amend FPRecipExponent to handle half-precision floating point
2019-03-09 20:08:01 -05:00
Lioncash
8036a54a74
frontend/ir/value: Add U16U32U64 type to represent floating point types
2019-03-09 20:08:01 -05:00
Lioncash
203678bd9e
A64: Implement SQSHRN, SQSHRUN, and UQSHRN's scalar variants
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These can just be implemented in terms of the vector variants for the
time being.
2019-03-08 03:23:56 -05:00
Lioncash
fb3847b044
A64: Amend prototypes of some SIMD scalar shift by immediate opcodes
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These take a vector for a destination.
2019-03-08 00:20:24 -05:00
Merry
40339b1278
Merge pull request #447 from lioncash/flag
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A64: Implement CFINV, RMIF, AXFlag and XAFlag
2019-03-07 16:17:13 +00:00
Lioncash
5b66ae2a5a
A64: Implement AXFlag and XAFlag
2019-03-06 18:39:19 -05:00
Lioncash
080d163d39
A64: Implement RMIF
2019-03-06 18:39:19 -05:00
Lioncash
9cd84c5149
A64: Implement CFINV
2019-03-06 18:39:12 -05:00
Merry
04f09eb644
Merge pull request #442 from lioncash/fcvtxn
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A64: Implement scalar and vector variants of FCVTXN
2019-03-06 20:27:59 +00:00
Lioncash
27af30d7c3
ir: Add A64-specific opcodes for getting and setting raw NZCV values
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This will be necessary to implement the flag manipulation and flag
format instructions.
2019-03-06 14:17:27 -05:00
Lioncash
cdfdd95e63
A64: Implement the vector version of FCVTXN
2019-03-06 12:05:24 -05:00
Lioncash
e3ba07971e
A64: Implement the scalar version of FCVTXN
2019-03-06 12:05:24 -05:00
Lioncash
f44cafe3ca
frontend/ir/ir_emitter: Alter parameters of FPDoubleToSingle() and FPSingleToDouble() to pass along desired rounding mode
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This will be necessary to special-case the non-IEEE Von Neumann rounding
to odd rounding mode.
2019-03-06 12:05:20 -05:00
Merry
d0ae8dcf97
Merge pull request #446 from lioncash/sqshl
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A64: Implement scalar variants of SQSHL (register) and UQSHL (register)
2019-03-06 14:14:41 +00:00
Merry
948984bc94
Merge pull request #445 from lioncash/sqrt
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A64: Implement single and double-precision vector variant of FSQRT
2019-03-06 14:14:21 +00:00
Merry
768a2a6973
Merge pull request #443 from lioncash/flag
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A64: Rearrange flag format/manipulation instructions
2019-03-06 14:13:59 +00:00
Lioncash
4429a0c8e5
A64: Implement UQSHL (register)'s scalar variant
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This can be implemented in terms of the vector variant.
2019-03-04 14:26:25 -05:00
Lioncash
a3eeb334fa
A64: Implement SQSHL (register)'s scalar variant
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We can implement this in terms of the vector variant.
2019-03-04 14:26:20 -05:00
Lioncash
16e6a8f343
A64: Implement single and double-precision vector variant of FSQRT
2019-03-04 13:37:27 -05:00
Lioncash
3e5a52cc66
frontend/ir: Add opcodes for vector square roots
2019-03-04 13:24:36 -05:00
Lioncash
d365d4083a
A64: Fall back to interpreting for FCADD and FCMLA half-precision variants
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Rather than straight-up treating them as undefined, we can fall back to an
interpreter in this case.
2019-03-04 12:23:57 -05:00
Lioncash
36eba63641
A64: Rearrange flag format/manipulation instructions
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Gives these instructions better categorical labeling.
2019-03-04 12:08:49 -05:00
Lioncash
7ae37bcc64
frontend/ir/microinstruction: Add missing cases for FPRecipExponent{32,64} for ReadsFromAndWritesToFPSRCumulativeExceptionBits()
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This was intended to be added within #437 , but was missed
2019-03-04 09:43:48 -05:00
Merry
f2fb7db668
Merge pull request #439 from lioncash/fcmla
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A64: Implement FCADD and FCMLA
2019-03-03 14:43:22 +00:00
Merry
73e230aa3f
Merge pull request #438 from lioncash/fmulx
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A64: Implement scalar double/single precision FMULX (by element)
2019-03-03 14:42:45 +00:00
Merry
456f2ec49f
Merge pull request #437 from lioncash/frecpx
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A64: Implement FRECPX (single, double precision)
2019-03-03 14:42:23 +00:00
Merry
8be7648e79
Merge pull request #436 from lioncash/no-alloc
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A64: Implement LDNP/STNP
2019-03-03 14:40:57 +00:00
Lioncash
dae46f0132
A64: Implement FRECPX (single, double precision)
2019-03-02 23:31:30 -05:00
Lioncash
7b004e7230
frontend/ir/ir_emitter: Add opcodes for floating point reciprocal exponents
2019-03-02 23:31:30 -05:00
Lioncash
9f556b8447
A64: Implement FCMLA
2019-03-02 22:50:17 -05:00
Lioncash
0d9cca04c0
A64: Implement FCADD
2019-03-02 22:49:57 -05:00
Lioncash
ccc3d5258e
A64: Implement scalar double/single precision FMULX (by element)
2019-03-02 21:12:09 -05:00
Lioncash
fc111fda0c
A64: Implement LDNP/STNP
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LDNP and STNP indicate that a memory access is non-temporal/streaming
(i.e. unlikely to be repeated), allowing data caching to not be
performed. However, given this is only a hint, we can treat these two
instructions as regular LDP and STP instructions for the time being.
2019-03-02 17:41:09 -05:00
Lioncash
02a70f3be1
translate_arm/coprocessor: Minor tidying up
2019-03-01 03:15:43 -05:00
Lioncash
c1f4241ca8
translate_arm/vfp2: Invert conditionals where applicable
2019-03-01 03:10:18 -05:00
Lioncash
797fca0125
translate_arm/synchronization: Invert conditionals where applicable
2019-03-01 02:23:24 -05:00
Lioncash
6a851dc412
translate_arm/status_register_access: Invert conditionals where applicable
2019-03-01 02:11:05 -05:00
Lioncash
18276e7c66
translate_arm/saturated: Invert conditionals where applicable
2019-03-01 02:05:30 -05:00
Lioncash
55fff7b2f6
translate_arm/reversal: Invert conditionals where applicable
2019-03-01 01:51:47 -05:00
Lioncash
a6a9fbcc48
translate_arm/parallel: Invert conditionals where applicable
2019-03-01 01:49:30 -05:00
