8 Commits

Author SHA1 Message Date
MerryMage
d333b5dcee A64: Implement ADD (vector, vector) 2018-01-21 17:56:27 +00:00
MerryMage
9ab130490b A64: Add ExceptionRaised IR instruction
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2018-01-13 18:06:06 +00:00
MerryMage
16e50ca0db A32: Implement load stores (immediate) 2018-01-10 01:30:30 +00:00
MerryMage
f19f014a42 A64: Implement SVC 2018-01-09 18:57:07 +00:00
MerryMage
305456b407 A64: Implement compare and branch 2018-01-09 18:57:06 +00:00
MerryMage
c4abd1fda1 A64: Implement branch (register) 2018-01-09 18:57:06 +00:00
MerryMage
8a8dcad250 A64: Implement addsub instructions 2018-01-09 18:57:06 +00:00
MerryMage
ef6fd92fed A64: Backend framework 2018-01-09 18:57:06 +00:00