Lioncash
3447c82656
translate: Return by bool in helpers where applicable
...
Gets rid of a bit of duplication regarding the early-out cases and makes
all helpers functions consistent (previously some had a return type of
bool, while others had a return type of void).
2020-04-22 20:46:21 +01:00
Lioncash
2d269fdcc7
simd_shift_by_immediate: Merge signed/unsigned helper functions
...
Gets rid of a little more code duplication.
2020-04-22 20:46:16 +01:00
Lioncash
2db032ac83
A64: Implement SRI (vector)
2020-04-22 20:46:16 +01:00
Lioncash
11005cfe26
A64: Implement SLI (vector)
2020-04-22 20:46:16 +01:00
Lioncash
e3d9bf55e7
A64: Implement SRSRA (vector)
2020-04-22 20:46:16 +01:00
Lioncash
bc6016cad7
A64: Implement SRSHR (vector)
2020-04-22 20:46:16 +01:00
Lioncash
4b3d70de5f
simd_shift_by_immediate: Factor out common code in shift instructions
...
Gets rid of partial duplication of the same code for instructions that only have a small behavior difference to them.
e.g. The only difference between SSHR and SSRA is that SSRA adds an accumulator before storing the result.
2020-04-22 20:46:16 +01:00
Lioncash
56803f5203
A64: Implement URSRA (vector)
2020-04-22 20:46:16 +01:00
Lioncash
8afdf4b23d
A64: Implement URSHR (vector)
2020-04-22 20:46:16 +01:00
Lioncash
16613ee066
A64: Implement RSHRN/RSHRN2
2020-04-22 20:46:15 +01:00
Lioncash
937990fd2a
A64: Implement SHRN/SHRN2
2020-04-22 20:46:15 +01:00
MerryMage
5f77ab28ee
A64: Implement SSHLL, SSHLL2
2020-04-22 20:46:14 +01:00
MerryMage
bd106c3ae7
A64: Implement SIMD instruction SSRA, vector variant
2020-04-22 20:46:14 +01:00
MerryMage
f58aba9871
A64: Implement SIMD instruction SSHR, vector variant
2020-04-22 20:46:14 +01:00
MerryMage
3f93c77ace
A64: Implement SIMD instruction USRA, vector variant
2020-04-22 20:46:13 +01:00
MerryMage
fb9d20f27f
A64: Implement SIMD instruction USHR, vector variant
2020-04-22 20:46:13 +01:00
MerryMage
7ff280827b
A64: Implement SIMD instructions USHLL, USHLL2
2020-04-22 20:46:13 +01:00
MerryMage
d3a4e1efe2
IR: Vector instructions now take esize argument in emitter
2020-04-22 20:46:13 +01:00
MerryMage
1d0cd95b23
A64: Implement SIMD instruction SHL
2020-04-22 20:46:13 +01:00
