Citra-emu/dynarmic-android
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526 Commits

Author SHA1 Message Date
Lioncash
62d49b32c2 A64: Implement UABD 2018-04-02 19:08:20 +01:00
Lioncash
734447ef3d ir: Add opcodes for performing vector unsigned absolute differences 2018-04-02 19:08:20 +01:00
Lioncash
5baa22b26b ir_emitter: Make immediate member functions const qualified 
These don't modify class state
 2018-04-02 19:07:26 +01:00
Lioncash
1e8fe95cc4 IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords 
I should have added this when I introduced the functions for interleaving
low-order equivalents for consistency in the interface.
 2018-03-31 11:01:38 +01:00
Lioncash
3970a8856d A64: Implement SHA1H 
This is a fairly trivial instruction it's essentially:

result = ROL(data, 30);
 2018-03-31 10:59:49 +01:00
Lioncash
a94f321f69 A64: NOP immediate variant of PRFM 
Makes behavior identical to the literal variant of PRFM. Given this is simply a hint instruction,
this is valid behavior. The upside is that we don't fall back to Unicorn unnecessarily whenever
the instruction is encountered.
 2018-03-29 20:59:43 +01:00
Lioncash
6f03fddee5 A64: system: Use an enum class for MRS/MSR register encodings 
Reduces the need to manually write out the register bit encodings repeatedly.
 2018-03-29 12:44:37 +01:00
Lioncash
25a0204203 A64: Implement REV64 2018-03-23 17:34:59 +00:00
Lioncash
e537985584 A64: Implement REV32 (vector) 2018-03-21 15:40:03 +00:00
Lioncash
f62a258945 ir: Add IR opcodes for emitting vector shuffles 
This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes)
as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
 2018-03-21 15:40:03 +00:00
Lioncash
20a59a9721 A64: Implement REV16 (vector) 2018-03-16 18:01:33 +00:00
Lioncash
fd21b58c3d A64: Implement EOR3 and BCAX 2018-03-13 23:20:58 +00:00
MerryMage
6b4c6b06a9 impl: Update PC when raising exception 2018-02-21 21:02:42 +00:00
MerryMage
7a1313aa24 A64: Implement FDIV (vector) 2018-02-21 15:03:36 +00:00
MerryMage
b2d781da3a system: Raise exception for YIELD, WFE, WFI, SEV, SEVL 2018-02-20 20:31:56 +00:00
MerryMage
b277bf5061 Correct FPSR and FPCR 2018-02-20 20:31:17 +00:00
MerryMage
7673933a9b A64: Implement USHL 2018-02-20 19:48:15 +00:00
MerryMage
8d0e558271 A64: Implement UCVTF (vector, integer), scalar variant 2018-02-20 19:11:35 +00:00
MerryMage
da9a4f8877 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 2018-02-20 18:45:28 +00:00
MerryMage
747968416f A64: Implement system register TPIDR_EL0 2018-02-20 17:56:20 +00:00
MerryMage
0fd75fd9cb A64: Implement system registers FPCR and FPSR 2018-02-20 17:38:29 +00:00
MerryMage
31e370cdf4 A64: Implement system register CNTPCT_EL0 2018-02-20 16:56:05 +00:00
MerryMage
9a88fd3340 A64: Implement system register CTR_EL0 2018-02-20 16:44:13 +00:00
MerryMage
1d16896d25 A64: Implement NEG (vector) 2018-02-20 15:41:07 +00:00
MerryMage
3184edf4a9 IR: Add IR instruction ZeroVector 2018-02-20 15:41:07 +00:00
MerryMage
567eb1a2f1 A64: Implement FMINNM (scalar) 2018-02-20 14:14:40 +00:00
MerryMage
c6d8fa1d36 A64: Implement FMAXNM (scalar) 2018-02-20 14:05:14 +00:00
MerryMage
a3747cb01c A64: Implement ADDP (scalar) 2018-02-18 23:55:38 +00:00
MerryMage
dd0452a435 A64: Implement DUP (element), scalar variant 2018-02-18 18:58:01 +00:00
MerryMage
40eb9c3253 A64: Implement FMAX (scalar), FMIN (scalar) 2018-02-18 13:49:23 +00:00
MerryMage
be292a819c A64: Implement FSQRT (scalar) 2018-02-18 13:18:22 +00:00
MerryMage
e585e1d49e T32: Add initial decoder list 2018-02-14 19:29:19 +00:00
MerryMage
1598af4f12 simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector) 2018-02-13 19:01:47 +00:00
MerryMage
029ae11040 A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero) 2018-02-13 19:01:21 +00:00
MerryMage
91483ab975 decoder/a64: Rearrange SIMD two-register misc decoders 2018-02-13 18:51:43 +00:00
MerryMage
9158534048 A64: Implement CMGE (register) 2018-02-13 18:29:54 +00:00
MerryMage
41e421bf0b A64: Implement CMHI, CMHS 2018-02-13 18:20:18 +00:00
MerryMage
324810cfad IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned} 2018-02-13 18:20:00 +00:00
MerryMage
89007194a7 A64: Implement SMAX, SMIN, UMAX, UMIN 2018-02-13 17:57:07 +00:00
MerryMage
2880eb3da1 IR: Implement Vector{Max,Min}{Signed,Unsigned} 2018-02-13 17:56:46 +00:00
MerryMage
7d8543b70e A64: Implement CMGT (register) 2018-02-13 15:47:52 +00:00
MerryMage
6d4f14e876 IR: Implement VectorGreaterSigned 2018-02-13 15:47:52 +00:00
MerryMage
9527d52c49 Exclusive fixups 
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
 2018-02-13 15:47:52 +00:00
MerryMage
229ff47738 Merge branch 'feature/exclusive-mem' 2018-02-13 12:53:29 +00:00
MerryMage
43f27b3e15 A64: Implement STXP, STLXP, LDXP, LDAXP 2018-02-13 12:50:50 +00:00
MerryMage
11eb8c2bea A64: Implement CLREX 2018-02-13 12:31:16 +00:00
MerryMage
22285842af A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR 2018-02-13 12:30:58 +00:00
MerryMage
7a161ed35c A64: Partially implement MRS 2018-02-12 00:06:44 +00:00
MerryMage
b733479b5e A64: Implement DSB, DMB 2018-02-11 23:27:28 +00:00
MerryMage
1ba2642742 Implement DC instructions 2018-02-11 23:12:28 +00:00