MerryMage
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63d3a1cc1c
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A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
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2018-02-06 18:30:36 +00:00 |
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MerryMage
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59a84ed966
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A64: Implement BIC (vector, register)
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2018-02-06 17:57:50 +00:00 |
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MerryMage
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8530f52729
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A64: Implement FMOV (general)
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2018-02-05 21:44:20 +00:00 |
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MerryMage
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37b4840c6f
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A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2018-02-05 15:41:41 +00:00 |
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MerryMage
|
a785d4fa66
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A64: Implement FCCMPE
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2018-02-05 12:26:19 +00:00 |
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MerryMage
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d2a2562a25
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A64: Implement FCCMP
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2018-02-05 12:26:19 +00:00 |
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Lioncash
|
d86b8fc40d
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A64: Implement FMOV (register)
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2018-02-05 09:34:47 +00:00 |
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MerryMage
|
97a742a7c0
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A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2018-02-05 01:12:19 +00:00 |
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Lioncash
|
e619902ee5
|
A64: Implement CCMP (immediate)
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2018-02-05 00:45:39 +00:00 |
|
Lioncash
|
d91989a014
|
A64: Implement CCMN (immediate)
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2018-02-05 00:45:39 +00:00 |
|
Lioncash
|
d5e58ac771
|
A64: Implement CCMP (register)
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2018-02-05 00:45:39 +00:00 |
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MerryMage
|
10594c7adb
|
A64: Implement CCMN (register)
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2018-02-04 23:11:07 +00:00 |
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MerryMage
|
c3d2edf8ee
|
A64: Implement FNEG
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2018-02-04 13:44:33 +00:00 |
|
MerryMage
|
ad5fe6dc43
|
A64: Implement FABS
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2018-02-04 13:43:47 +00:00 |
|
MerryMage
|
107bd14a43
|
A64: Implement FCSEL
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2018-02-04 13:40:37 +00:00 |
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MerryMage
|
9db02bb4db
|
A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
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2018-02-04 13:21:31 +00:00 |
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MerryMage
|
f87ecad5a4
|
A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2018-02-04 13:09:57 +00:00 |
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MerryMage
|
e5ce22aabc
|
A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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2018-02-04 12:49:40 +00:00 |
|
Lioncash
|
ccf9493653
|
A64: Implement AESD
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2018-02-03 23:11:46 +00:00 |
|
Lioncash
|
33bc59c55a
|
A64: Implement AESE
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2018-02-03 23:11:46 +00:00 |
|
MerryMage
|
2262b08a04
|
A64: Implement INS (general)
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2018-02-03 13:07:00 +00:00 |
|
MerryMage
|
3c140141db
|
A64: Implement INS (element)
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2018-02-03 13:03:50 +00:00 |
|
MerryMage
|
af5fb0a1a0
|
A64: Implement SMOV
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2018-02-03 12:58:19 +00:00 |
|
MerryMage
|
818b9a4673
|
A64: Implement UMOV
|
2018-02-03 12:55:53 +00:00 |
|
MerryMage
|
64e37de179
|
A64: Implement FCVT
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2018-02-03 01:23:11 +00:00 |
|
MerryMage
|
2fd70e56ce
|
A64: Implement FMOV (scalar, immediate)
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2018-02-03 00:52:48 +00:00 |
|
MerryMage
|
567c1b57fc
|
A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
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2018-02-02 22:39:24 +00:00 |
|
MerryMage
|
c42ca435ba
|
A64: Implement FCMP, FCMPE
|
2018-02-02 22:25:51 +00:00 |
|
MerryMage
|
4728257d4e
|
A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
|
2018-02-02 22:04:09 +00:00 |
|
MerryMage
|
6d9adb668e
|
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2018-02-02 21:10:30 +00:00 |
|
Lioncash
|
b608979be9
|
A64: Implement AESIMC and AESMC
|
2018-02-02 17:35:16 +00:00 |
|
Lioncash
|
7fb386aa1c
|
A64: Implement CRC32
|
2018-01-29 17:06:17 +00:00 |
|
Lioncash
|
0216cbd2a5
|
A64: Implement CRC32C
|
2018-01-28 12:20:56 +00:00 |
|
Lioncash
|
dbddb4858a
|
A64: Implement EXTR
|
2018-01-26 22:07:48 +00:00 |
|
MerryMage
|
bda9148e71
|
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
|
2018-01-26 18:39:19 +00:00 |
|
MerryMage
|
06bea0ceaa
|
A64: Implement CMEQ (register, vector)
|
2018-01-26 01:52:42 +00:00 |
|
Fernando Sahmkow
|
5ffd11d140
|
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
|
2018-01-26 00:57:56 +00:00 |
|
James Rowe
|
76aaa84687
|
A64: Fix bugs and address review comments
|
2018-01-25 17:46:14 +00:00 |
|
James Rowe
|
ddb5b3469d
|
A64: Implement Load/Store register (unprivileged)
|
2018-01-25 17:46:14 +00:00 |
|
FernandoS27
|
d1664096f5
|
Implemented SDIV and UDIV instructions
|
2018-01-24 17:09:00 +00:00 |
|
MerryMage
|
8873d17db2
|
A64: Implement LDR/STR (immediate, SIMD&FP)
|
2018-01-24 16:28:18 +00:00 |
|
MerryMage
|
1db423b2ad
|
A64: Implement DUP (general)
|
2018-01-24 12:01:26 +00:00 |
|
Lioncash
|
0e5988258d
|
A64: Implement RBIT
|
2018-01-24 01:49:58 +00:00 |
|
MerryMage
|
d52cb2d0de
|
A64: Implement CLS
This is not the cleanest implementation.
|
2018-01-23 19:44:35 +00:00 |
|
MerryMage
|
24383e543b
|
A64: Implement ADDP (vector)
|
2018-01-23 17:46:28 +00:00 |
|
Lioncash
|
bd00d9bc80
|
A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL
|
2018-01-23 16:08:05 +00:00 |
|
Lioncash
|
768e5bcf9c
|
A64: Implement MADD and MSUB
|
2018-01-23 16:08:05 +00:00 |
|
Lioncash
|
ffaf837e58
|
A64: Implement CLZ
|
2018-01-23 11:55:09 +00:00 |
|
Lioncash
|
efa67caf5f
|
A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
Truly the most difficult A64 instructions to implement.
|
2018-01-22 11:54:12 +00:00 |
|
Lioncash
|
692cd6f27b
|
A64: Implement ASRV, LSLV, LSRV, and RORV
|
2018-01-22 11:51:46 +00:00 |
|