Lioncash
64de80839e
A64/impl: Reorganize peculiar void use in V_scalar
...
To a reader this might look particularly strange, given the function
itself has a void return value, but this is actually valid, given the
function in the return statement also has a void return value.
This instead alters it to be a little easier to parse and potentially be
a little less confusing at a glance.
2020-04-22 21:01:43 +01:00
V.Kalyuzhny
764a93bf5a
Switch boost::optional to std::optional
2020-04-22 20:57:37 +01:00
MerryMage
d4c37a68a8
A64/translate: VectorZeroUpper for V(64) stores
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Ensures correctness.
2020-04-22 20:55:05 +01:00
Lioncash
3acd9c9200
translate: zero extend result in Vpart when storing to lower part of vector
2020-04-22 20:46:17 +01:00
Lioncash
80e005e5b5
A64/translate: Amend I() to also handle u8 and u16 immediates
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This is necessary for instructions like SRSHR, and other related instructions.
2020-04-22 20:46:15 +01:00
MerryMage
be5047c7c2
impl: Update PC when raising exception
2020-04-22 20:46:15 +01:00
MerryMage
fd075d8d68
system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
2020-04-22 20:46:15 +01:00
MerryMage
b7a2c1a7df
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2020-04-22 20:46:14 +01:00
MerryMage
5edd623b9d
Implement DC instructions
2020-04-22 20:46:14 +01:00
MerryMage
e7041d7196
A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
2020-04-22 20:46:14 +01:00
MerryMage
a455ff70c9
decoder/a64: Don't rearrange unrelated decoders
2020-04-22 20:46:14 +01:00
MerryMage
653c82d8f0
impl: Improve Vpart setter
2020-04-22 20:46:14 +01:00
MerryMage
e858ce0b35
A64: Implement SIMD instructions XTN, XTN2
2020-04-22 20:46:13 +01:00
MerryMage
7ff280827b
A64: Implement SIMD instructions USHLL, USHLL2
2020-04-22 20:46:13 +01:00
MerryMage
1d0cd95b23
A64: Implement SIMD instruction SHL
2020-04-22 20:46:13 +01:00
MerryMage
8ab7d8175c
impl: Add AdvSIMDExpandImm
2020-04-22 20:46:13 +01:00
MerryMage
dd88cee15a
translate/impl: Add Vpart
2020-04-22 20:46:13 +01:00
MerryMage
99d8ebe4d5
A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
2020-04-22 20:46:13 +01:00
MerryMage
d7044bc751
assert: Use fmt in ASSERT_MSG
2020-04-22 20:46:12 +01:00
MerryMage
b513b2ef05
IR: Implement IR instructions A64{Get,Set}S
2020-04-22 20:44:38 +01:00
Lioncash
67443efb62
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
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Makes namespacing a little less noisy
2020-04-22 20:44:38 +01:00
MerryMage
e1df7ae621
IR: Add IR instructions A64Memory{Read,Write}128
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This implementation only works on macOS and Linux.
2020-04-22 20:44:37 +01:00
MerryMage
a63fc6c89b
A64: Implement ADD (vector, vector)
2020-04-22 20:42:46 +01:00
MerryMage
0992987c98
A64: Add ExceptionRaised IR instruction
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The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2020-04-22 20:42:45 +01:00
MerryMage
aa74a8130b
Misc. fixups of MSVC build
2020-04-22 20:42:45 +01:00
MerryMage
25411da838
A32: Implement load stores (immediate)
2020-04-22 20:42:45 +01:00
MerryMage
0641445e51
A64: Implement logical
2020-04-22 20:42:45 +01:00
MerryMage
c09e69bb97
A64: Implement addsub instructions
2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0
A64: Implement ADD_shifted
2020-04-22 20:42:44 +01:00
