Lioncash
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6d0b58039e
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A64: Implement UHADD
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2018-05-07 16:39:17 +01:00 |
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Lioncash
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e4efd365fb
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A64: Implement SHADD
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2018-05-07 16:39:17 +01:00 |
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Lioncash
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1da4671b53
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ir: Add opcodes for performing halving adds
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2018-05-07 16:39:17 +01:00 |
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Lioncash
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7a066fb011
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disassembler_arm: Remove rotation helper function in favor of Common::RotateRight
Mildly reduces the amount of duplicated behavior
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2018-05-02 17:14:13 +01:00 |
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Lioncash
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8aa9a47a6a
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A64: Implement SSHL (scalar)
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2018-04-30 22:41:17 +01:00 |
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Lioncash
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8818d76212
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A64: Implement SSHL (vector)
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2018-04-30 22:41:17 +01:00 |
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Lioncash
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3e3ce37eb8
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backend_x64/ir: Amend generic LogicalVShift() template to also handle signed variants
Also adds IR opcodes to dispatch said variants
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2018-04-30 22:41:17 +01:00 |
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Lioncash
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fea1e6ca1f
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A64: Implement CMTST's scalar variant
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2018-04-28 19:17:38 +01:00 |
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Lioncash
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2a35b2a46a
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A64: Implement UZP1 and UZP2
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2018-04-26 08:49:51 +01:00 |
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Lioncash
|
9c2550ac72
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ir: Add opcodes for performing vector deinterleaving
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2018-04-26 08:49:51 +01:00 |
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Lioncash
|
4765503fc6
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A64: Implement FNEG (half-precision)
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2018-04-26 08:49:03 +01:00 |
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Lioncash
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96be76296e
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A64: Implement USHL (scalar)
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2018-04-24 08:15:00 +01:00 |
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Lioncash
|
8261911bd8
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A64: Implement FNEG (vector)
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2018-04-24 08:14:31 +01:00 |
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Lioncash
|
633e8e3ecd
|
A64: Implement RSUBHN/RSUBHN2
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2018-04-23 21:08:43 +01:00 |
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Lioncash
|
4dec013b09
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A64: Implement RADDHN/RADDHN2
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2018-04-23 21:08:43 +01:00 |
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Lioncash
|
7fb04ccb36
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A64: Implement XAR
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2018-04-23 16:05:40 +01:00 |
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Lioncash
|
db29d68a2d
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simd_two_register_misc: Factor out common comparison code
Gets rid of a tiny bit of duplicated code.
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2018-04-23 16:04:58 +01:00 |
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Lioncash
|
1692e26c2e
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A64: Implement CMLE (zero)'s vector variant
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2018-04-23 16:04:58 +01:00 |
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Lioncash
|
21936a82aa
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A64: Implement CMTST (vector)
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2018-04-23 16:04:40 +01:00 |
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Lioncash
|
4f27764191
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A64: Implement ADDHN{2} and SUBHN{2}
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2018-04-21 08:58:16 +01:00 |
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Lioncash
|
1791114ab1
|
translate: zero extend result in Vpart when storing to lower part of vector
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2018-04-21 08:58:16 +01:00 |
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Lioncash
|
f6e624e9ea
|
A64: Implement CMLE (zero)'s scalar variant
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2018-04-20 17:31:07 +01:00 |
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Lioncash
|
41a3e87c15
|
A64: Implement CMLT (zero)'s scalar single/double-precision variant
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2018-04-20 15:48:50 +01:00 |
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Lioncash
|
51912ca6ab
|
A64: Implement SHA512H2
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2018-04-20 07:29:26 +01:00 |
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Lioncash
|
4655f78ec2
|
A64: Implement SHA512H
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2018-04-20 07:29:26 +01:00 |
|
Lioncash
|
3a52275611
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A64: Handle S32->F32 case for SCVTF (vector)
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2018-04-19 21:09:42 +01:00 |
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Lioncash
|
230e954e5c
|
IR: Add opcode for packed word->f32 conversions
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2018-04-19 21:09:42 +01:00 |
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Lioncash
|
f24cfba5c2
|
A64: Implement SHA512SU1
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2018-04-19 19:51:31 +01:00 |
|
Lioncash
|
e3412d9779
|
A64: Implement SHA512SU0
|
2018-04-19 19:51:31 +01:00 |
|
Lioncash
|
cc76802990
|
A64: Implement SHA256H and SHA256H2
|
2018-04-19 19:50:17 +01:00 |
|
MerryMage
|
b5585baefb
|
A64: Implement SCVTF (vector, integer), scalar varaint
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2018-04-19 19:48:45 +01:00 |
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MerryMage
|
badc7ac467
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impl: Reorganize scalar two-register misc instructions
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2018-04-19 19:48:45 +01:00 |
|
Lioncash
|
d53decf9e1
|
A64: Implement SHA256SU1
|
2018-04-19 08:40:55 +01:00 |
|
Lioncash
|
62be988507
|
simd_two_register_misc: Add missing zeroing of the vector for CMGT and CMLT
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2018-04-19 08:39:56 +01:00 |
|
Lioncash
|
cd5fee6746
|
A64: Implement CMGE (zero)'s vector variant
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2018-04-19 08:39:56 +01:00 |
|
Lioncash
|
da99e1fdaa
|
A64: Implement MLS (by element)
|
2018-04-19 08:39:25 +01:00 |
|
Lioncash
|
8920238d59
|
A64: Implement MUL (by element)
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2018-04-19 08:39:25 +01:00 |
|
MerryMage
|
68d6a1276b
|
A64: Implement MLA (by element)
|
2018-04-19 00:04:52 +01:00 |
|
Lioncash
|
7340c36ae0
|
A64: Implement ABS (scalar)
|
2018-04-19 00:03:08 +01:00 |
|
Lioncash
|
c196c73e17
|
A64: Implement SHA256SU0
|
2018-04-19 00:00:39 +01:00 |
|
Lioncash
|
cb3b885025
|
A64: Implement SHA1M
|
2018-04-16 07:47:22 +01:00 |
|
Lioncash
|
4381ded969
|
A64: Implement SHA1P
|
2018-04-16 07:47:22 +01:00 |
|
Lioncash
|
dc5c2508a5
|
A64: Implement scalar variants of CMEQ, CMGT, and CMGE zero comparison instructions
These can trivially use the ScalarCompare helper function.
|
2018-04-15 13:38:42 +01:00 |
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Lioncash
|
3a71801f10
|
A64: Implement scalar variant of NEG
|
2018-04-15 13:37:07 +01:00 |
|
Lioncash
|
f8e387f13f
|
simd: Relocate REV16, REV32 and REV64 vector variants to the proper file
These aren't scalar instruction variants.
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2018-04-15 13:37:07 +01:00 |
|
Lioncash
|
e23f6b666e
|
A64: Implement CMEQ (register, scalar)
|
2018-04-15 11:31:20 +01:00 |
|
Lioncash
|
5f879af788
|
A64: Implement CMHS (register, scalar)
|
2018-04-15 11:31:20 +01:00 |
|
Lioncash
|
41e4b3e286
|
A64: Implement CMHI (register, scalar)
|
2018-04-15 11:31:20 +01:00 |
|
Lioncash
|
03f6247239
|
A64: Implement CMGE (register, scalar)
|
2018-04-15 11:31:20 +01:00 |
|
Lioncash
|
62ddc0631e
|
A64: Implement CMGT (register, scalar)
|
2018-04-15 11:31:20 +01:00 |
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