Lioncash
1da4671b53
ir: Add opcodes for performing halving adds
2018-05-07 16:39:17 +01:00
Lioncash
3e3ce37eb8
backend_x64/ir: Amend generic LogicalVShift() template to also handle signed variants
...
Also adds IR opcodes to dispatch said variants
2018-04-30 22:41:17 +01:00
Lioncash
9c2550ac72
ir: Add opcodes for performing vector deinterleaving
2018-04-26 08:49:51 +01:00
Lioncash
230e954e5c
IR: Add opcode for packed word->f32 conversions
2018-04-19 21:09:42 +01:00
Lioncash
f921005a70
ir: Add opcode for reversing bits in a vector
2018-04-03 21:18:03 +01:00
Lioncash
032b09cbdf
ir: Add opcodes for performing vector absolute values
2018-04-03 07:49:08 +01:00
MerryMage
14d3d72aac
IR: Implement VectorExtract, VectorExtractLower IR instructions
2018-04-02 21:52:46 +01:00
MerryMage
c56b6d0981
A64: Implement FMUL (vector)
2018-04-02 21:02:57 +01:00
Lioncash
734447ef3d
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-02 19:08:20 +01:00
Lioncash
1e8fe95cc4
IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords
...
I should have added this when I introduced the functions for interleaving
low-order equivalents for consistency in the interface.
2018-03-31 11:01:38 +01:00
Lioncash
f62a258945
ir: Add IR opcodes for emitting vector shuffles
...
This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes)
as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
2018-03-21 15:40:03 +00:00
MerryMage
7a1313aa24
A64: Implement FDIV (vector)
2018-02-21 15:03:36 +00:00
MerryMage
7673933a9b
A64: Implement USHL
2018-02-20 19:48:15 +00:00
MerryMage
747968416f
A64: Implement system register TPIDR_EL0
2018-02-20 17:56:20 +00:00
MerryMage
0fd75fd9cb
A64: Implement system registers FPCR and FPSR
2018-02-20 17:38:29 +00:00
MerryMage
31e370cdf4
A64: Implement system register CNTPCT_EL0
2018-02-20 16:56:05 +00:00
MerryMage
9a88fd3340
A64: Implement system register CTR_EL0
2018-02-20 16:44:13 +00:00
MerryMage
3184edf4a9
IR: Add IR instruction ZeroVector
2018-02-20 15:41:07 +00:00
MerryMage
567eb1a2f1
A64: Implement FMINNM (scalar)
2018-02-20 14:14:40 +00:00
MerryMage
c6d8fa1d36
A64: Implement FMAXNM (scalar)
2018-02-20 14:05:14 +00:00
MerryMage
2880eb3da1
IR: Implement Vector{Max,Min}{Signed,Unsigned}
2018-02-13 17:56:46 +00:00
MerryMage
6d4f14e876
IR: Implement VectorGreaterSigned
2018-02-13 15:47:52 +00:00
MerryMage
43f27b3e15
A64: Implement STXP, STLXP, LDXP, LDAXP
2018-02-13 12:50:50 +00:00
MerryMage
22285842af
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 12:30:58 +00:00
MerryMage
7a161ed35c
A64: Partially implement MRS
2018-02-12 00:06:44 +00:00
MerryMage
b733479b5e
A64: Implement DSB, DMB
2018-02-11 23:27:28 +00:00
MerryMage
1ba2642742
Implement DC instructions
2018-02-11 23:12:28 +00:00
MerryMage
1b836b6deb
IR: Implement FPMax, FPMin
2018-02-11 16:43:47 +00:00
MerryMage
24def19cd7
IR: Implement FPVectorAdd
2018-02-11 16:29:48 +00:00
MerryMage
a7e4202828
IR: Implement VectorSignExtend
2018-02-11 16:24:33 +00:00
MerryMage
8c6fce20d2
IR: Implement FPVectorSub
2018-02-11 12:17:53 +00:00
MerryMage
c2c9ea85a5
IR: Implement VectorPopulationCount
2018-02-11 11:52:44 +00:00
MerryMage
80fce9c4b9
IR: Implement VectorMultiply
2018-02-11 10:18:29 +00:00
MerryMage
a5299d0be5
IR: Implement VectorArithmeticShiftRight
2018-02-10 23:27:46 +00:00
MerryMage
dc9785bdcd
IR: Implement VectorNarrow
2018-02-10 17:01:33 +00:00
MerryMage
d9f803924e
IR: Implement VectorSub
2018-02-10 11:25:50 +00:00
MerryMage
e6a0a4d8ce
IR: Implement VectorLogicalShiftRight
2018-02-10 11:05:22 +00:00
MerryMage
670b47149e
IR: Implement VectorZeroExtend
2018-02-10 10:35:14 +00:00
MerryMage
570911e693
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:54 +00:00
MerryMage
e03a9fed98
opcodes: Sort vector IR opcodes alphabetically
2018-02-10 09:15:01 +00:00
Lioncash
25e7c94995
A64: Implement ZIP1
2018-02-07 12:06:49 +00:00
FernandoS27
c882e6819d
Implemented UMULH and SMULH instructions
2018-02-06 23:59:24 +00:00
MerryMage
37a9472f81
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
2018-02-05 12:26:19 +00:00
MerryMage
ee8726a8ba
IR: Add ConditionalSelectNZCV instruction
2018-02-04 23:08:43 +00:00
Lioncash
ccf9493653
A64: Implement AESD
2018-02-03 23:11:46 +00:00
Lioncash
33bc59c55a
A64: Implement AESE
2018-02-03 23:11:46 +00:00
MerryMage
a7209dc2f7
IR: Add IR instruction NZCVFromPackedFlags
...
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
2018-02-03 13:41:36 +00:00
MerryMage
6d9adb668e
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
2018-02-02 21:10:30 +00:00
MerryMage
cc40b83ed0
IR: Implement VectorSetElement{8,16,32,64}
2018-02-02 21:00:12 +00:00
Lioncash
b608979be9
A64: Implement AESIMC and AESMC
2018-02-02 17:35:16 +00:00
