MerryMage
8f46c26d26
IR: Initial implementation of FPVectorRoundInt
2018-07-30 13:31:51 +01:00
MerryMage
ce58863903
IR: Generalise SignedSaturated{Add,Sub} to support more bitwidths
2018-07-30 11:01:36 +01:00
Lioncash
1dfb29fc14
ir: Add opcodes for vector paired maximum and minimums
...
For the time being, we can just do a naive implementation which avoids
falling back to the interpreter a bit. Horizontal operations aren't
necessarily x86 SIMD's forte anyways.
2018-07-30 08:40:32 +01:00
Lioncash
aae22eec26
ir: Add opcodes for performing scalar integral min/max
2018-07-30 08:39:33 +01:00
Lioncash
6ef3af3bc9
A64: Implement PMULL{2}
2018-07-29 10:04:58 +01:00
Lioncash
656a4042a2
ir: Add opcode for performing polynomial multiplication
2018-07-26 16:16:30 +01:00
MerryMage
0f9bc2d391
IR: Implement FPVectorTo{Signed,Unsigned}Fixed
2018-07-26 12:48:36 +01:00
MerryMage
76f0ca04d6
IR: Implement FPVector{Max,Min}
2018-07-26 09:31:56 +01:00
MerryMage
2d2ca5ebc1
IR: Implement FPRecipStepFused, FPVectorRecipStepFused
2018-07-25 19:14:23 +01:00
MerryMage
c5a14ab21b
IR: Implement FPVectorRecipEstimate
2018-07-25 18:55:40 +01:00
MerryMage
186e52ca50
IR: Implement FPRecipEstimate
2018-07-25 18:36:40 +01:00
MerryMage
b1e3616de2
IR: Implement FPVectorNeg
2018-07-25 13:25:35 +01:00
MerryMage
93eeb25fac
IR: Implement FPVectorMulAdd
2018-07-25 13:19:48 +01:00
MerryMage
ff025e88d0
IR: Implement A64OrQC
2018-07-24 19:04:40 +01:00
MerryMage
759289ec5c
A64: Implement UQXTN (vector)
2018-07-24 18:31:32 +01:00
MerryMage
0682353626
A64: Implement SQXTN (vector)
2018-07-24 17:59:14 +01:00
MerryMage
d9b59c69de
A64: Implement SQXTUN
2018-07-24 16:32:10 +01:00
MerryMage
f7052ae04d
A64: Implement FRSQRTS (vector), single/double variant
2018-07-23 22:58:52 +01:00
MerryMage
0925ef6248
A64: Implement FRSQRTE (vector), single/double variant
2018-07-23 22:46:12 +01:00
MerryMage
4ef864e81c
IR: Implement FPRSqrtStepFused
2018-07-23 22:05:17 +01:00
MerryMage
7ed089fd8e
IR: Implement FPRSqrtEstimate
2018-07-22 18:35:43 +01:00
MerryMage
39958434b6
A64: Implement FABD in terms of existing IR instructions
...
Fixes NaN issue. Closes #306 .
2018-07-16 16:51:16 +01:00
MerryMage
48166d80cd
IR: Implement FPRoundInt
2018-07-16 14:10:53 +01:00
MerryMage
59e78dc57e
A64: Implement FADDP (vector)
2018-07-15 22:49:58 +01:00
MerryMage
dfdec797e3
A64: Implement SADDLP
2018-07-15 18:50:09 +01:00
MerryMage
3bb6a432d8
A64: Implement UADDLP
2018-07-15 18:26:54 +01:00
MerryMage
2f567fe003
IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64}
...
This implementation just falls-back to the software floating point implementation.
2018-07-15 15:37:29 +01:00
Lioncash
d921423160
ir: Add opcodes for vector conversion of u32/u64 to floating-point
2018-07-15 12:46:35 +01:00
Lioncash
0b2c6c4eb8
ir: Add opcodes for converting S64 and U64 to single-precision floating-point values
2018-07-15 12:29:26 +01:00
Lioncash
979b6f39f1
ir: Add opcodes for converting S64 and U64 to double-precision values
2018-07-10 00:15:19 +01:00
Lioncash
c566307b87
ir: Extend FPVectorAbs opcode to also handle 16-bit elements for FP16
2018-07-07 21:42:42 +01:00
Lioncash
f769be89dc
ir: Add opcodes for performing vector absolute floating-point values
...
This will be usable for implementing FACGE and FACGT
2018-07-07 14:49:47 +01:00
Lioncash
cfeda05286
ir: Add opcode for performing FP vector absolute differences
2018-06-09 10:28:45 +01:00
MerryMage
f05cb06244
IR: Implement FPMulAdd
2018-06-08 15:23:35 +01:00
Lioncash
21a38854e5
ir: Add opcode for floating-point GE and GT comparisons
...
The rest of the comparisons can be implemented in terms of these two
2018-06-05 17:21:35 +01:00
Lioncash
239d2243c0
ir: Add opcodes for floating-point vector equalities
2018-06-03 21:49:06 +01:00
Lioncash
2652e92928
ir: Add opcodes for performing rounding halving adds
2018-05-26 11:48:56 +01:00
Lioncash
d7951233bd
ir: Add opcodes for signed absolute differences
2018-05-12 11:16:42 +01:00
Lioncash
b166981ff5
ir: Add opcode to perform the vector conversion S64->F64
...
Unfortunately x86 prior to AVX-512 doesn't really give us any convenient instruction to do the work for us
2018-05-08 18:14:50 +01:00
Lioncash
a0e3943ade
ir: Add opcodes for performing vector halving subtracts
2018-05-07 19:04:10 +01:00
Lioncash
284afd18cb
ir: Add an opcode for doing an SM4 lookup table query
2018-05-07 19:01:22 +01:00
Lioncash
1da4671b53
ir: Add opcodes for performing halving adds
2018-05-07 16:39:17 +01:00
Lioncash
3e3ce37eb8
backend_x64/ir: Amend generic LogicalVShift() template to also handle signed variants
...
Also adds IR opcodes to dispatch said variants
2018-04-30 22:41:17 +01:00
Lioncash
9c2550ac72
ir: Add opcodes for performing vector deinterleaving
2018-04-26 08:49:51 +01:00
Lioncash
230e954e5c
IR: Add opcode for packed word->f32 conversions
2018-04-19 21:09:42 +01:00
Lioncash
f921005a70
ir: Add opcode for reversing bits in a vector
2018-04-03 21:18:03 +01:00
Lioncash
032b09cbdf
ir: Add opcodes for performing vector absolute values
2018-04-03 07:49:08 +01:00
MerryMage
14d3d72aac
IR: Implement VectorExtract, VectorExtractLower IR instructions
2018-04-02 21:52:46 +01:00
MerryMage
c56b6d0981
A64: Implement FMUL (vector)
2018-04-02 21:02:57 +01:00
Lioncash
734447ef3d
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-02 19:08:20 +01:00
