MerryMage
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e164ede4dc
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TranslateArm: Implement MRS, MSR (imm), MSR (reg)
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2016-08-15 11:50:49 +01:00 |
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bunnei
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30f3d869cc
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TranslateArm: Implement VPUSH and VPOP.
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2016-08-13 19:37:03 +01:00 |
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MerryMage
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1029fd27ce
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Update documentation (2016-08-12)
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2016-08-12 18:17:31 +01:00 |
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bunnei
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8e8db6e137
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TranslateArm: Implement VSTR.
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2016-08-10 15:01:23 +01:00 |
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MerryMage
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df39308e03
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TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
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2016-08-09 22:57:20 +01:00 |
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MerryMage
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d0d51ba346
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TranslateArm: Implement STM, STMDA, STMDB, STMIB
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2016-08-08 22:49:11 +01:00 |
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MerryMage
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85549d7ae2
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TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB
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2016-08-08 22:26:06 +01:00 |
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MerryMage
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3a465ba4a8
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VFP: Implement VLDR
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2016-08-07 19:59:35 +01:00 |
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MerryMage
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a2c2db277b
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VFP: Implement VMOV (all variants)
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2016-08-07 19:25:12 +01:00 |
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MerryMage
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0f412247ed
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VFP: Implement VSQRT
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2016-08-07 12:19:07 +01:00 |
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MerryMage
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cd8e7c0504
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VFP: Implement VNEG
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2016-08-07 12:04:21 +01:00 |
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MerryMage
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da33af5abe
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VFP: Implement VMLA, VMLS, VNMLA, VNMLS
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2016-08-07 11:49:06 +01:00 |
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MerryMage
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3f1345a1a5
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VFP: Implement VNMUL, VDIV
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2016-08-07 10:56:12 +01:00 |
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MerryMage
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12e7f2c359
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VFP: Implement VMUL
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2016-08-07 10:21:14 +01:00 |
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MerryMage
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97b5fa173f
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VFP: Implement VSUB
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2016-08-07 01:45:52 +01:00 |
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MerryMage
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ce6b5f8210
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VFP: Implement VABS
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2016-08-07 01:27:18 +01:00 |
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MerryMage
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4b31ea25a7
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VFP: Implement VADD.{F32,F64}
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2016-08-06 20:03:15 +01:00 |
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MerryMage
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8ff414ee0e
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Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top.
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2016-08-06 20:03:15 +01:00 |
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bunnei
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8c2300d477
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arm: Implement LDRD reg/imm instructions.
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2016-08-05 20:05:02 -04:00 |
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bunnei
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ec3a98cf95
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arm: Implement LDRH reg/imm instructions.
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2016-08-05 20:05:01 -04:00 |
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bunnei
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192a0fba7a
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arm: Implement LDRB reg/imm instructions.
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2016-08-05 20:05:00 -04:00 |
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bunnei
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dfb318f208
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arm: Implement STRD reg/imm instructions.
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2016-08-05 20:04:59 -04:00 |
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bunnei
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e931dc2496
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arm: Implement STRH reg/imm instructions.
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2016-08-05 20:04:58 -04:00 |
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bunnei
|
9f77662b24
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arm: Implement STRB reg/imm instructions.
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2016-08-05 20:04:57 -04:00 |
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bunnei
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caab1bbc7c
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arm: Implement STR reg/imm instructions.
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2016-08-05 20:04:56 -04:00 |
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bunnei
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b09ecb4532
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arm: Implement LDR reg/imm instructions.
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2016-08-05 20:04:55 -04:00 |
|
Tillmann Karras
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eb2e6e8bea
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Implement some multiplies
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2016-08-05 02:09:54 +01:00 |
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bunnei
|
691e4139fa
|
arm: Implement B/BL/BX instructions.
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2016-08-03 16:49:01 -04:00 |
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Tillmann Karras
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fc33f1d374
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Implement more instructions
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
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2016-08-03 00:47:17 +01:00 |
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Tillmann Karras
|
30a90295b9
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Implement data processing instructions
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST
The code could use some serious deduplication...
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2016-08-03 00:47:16 +01:00 |
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MerryMage
|
90d317b868
|
Implement memory endianness. Implement Thumb SETEND instruction.
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2016-07-20 15:34:17 +01:00 |
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MerryMage
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98bd7ff6a5
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Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support.
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2016-07-20 12:08:17 +01:00 |
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Merry
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95316b8443
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Merged in Subv/dynarmic/arm_mem_tests (pull request #4)
Added some fuzz tests for most cases of ARM Load/Store instructions
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2016-07-20 10:19:55 +01:00 |
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MerryMage
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3f11a149d7
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Implement Thumb Instructions: BLX (imm), BL (imm)
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2016-07-18 22:18:58 +01:00 |
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MerryMage
|
e0d6e28b67
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Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)
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2016-07-18 21:04:39 +01:00 |
|
Subv
|
ccc61472b9
|
Added format strings for ARM STRBT encodings A1 and A2
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2016-07-18 14:20:58 -05:00 |
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Subv
|
8617bf80a1
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Added format strings for ARM LDRBT encodings A1 and A2
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2016-07-18 14:18:39 -05:00 |
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Subv
|
5d5ea9325c
|
Added format strings for ARM STRT encodings A1 and A2
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2016-07-18 14:05:53 -05:00 |
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MerryMage
|
2363759c62
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Implement thumb STM, LDM. Fix thumb POP implementation for P=1.
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2016-07-18 20:05:35 +01:00 |
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Subv
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77761ba032
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Added the format strings for LDRT encodings A1 and A2.
|
2016-07-18 14:01:18 -05:00 |
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MerryMage
|
14dcb18bbe
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Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2)
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2016-07-18 18:48:08 +01:00 |
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MerryMage
|
a605a43ef9
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Implement Thumb Instructions: STRH (imm), LDRH (imm)
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2016-07-18 18:28:52 +01:00 |
|
MerryMage
|
f9755870bb
|
Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg)
|
2016-07-18 18:02:02 +01:00 |
|
MerryMage
|
dfef65d98f
|
Implement thumb POP instruction
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2016-07-18 17:37:48 +01:00 |
|
MerryMage
|
f7e3d7b8d2
|
Implement Thumb PUSH instruction
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2016-07-18 15:11:16 +01:00 |
|
MerryMage
|
9109b226af
|
Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm)
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2016-07-18 11:16:12 +01:00 |
|
MerryMage
|
c18a3eeab4
|
Better MSVC support
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
|
2016-07-18 10:38:22 +01:00 |
|
MerryMage
|
bf99ddd065
|
Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic
|
2016-07-18 10:33:52 +01:00 |
|
MerryMage
|
28a201da16
|
Implement Thumb ADR instruction
|
2016-07-18 09:25:33 +01:00 |
|
Subv
|
0cdf5fe751
|
Implemented ARM REV and REVSH instructions, with tests.
|
2016-07-17 14:45:42 -05:00 |
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