MerryMage
ee8726a8ba
IR: Add ConditionalSelectNZCV instruction
2018-02-04 23:08:43 +00:00
Lioncash
ccf9493653
A64: Implement AESD
2018-02-03 23:11:46 +00:00
Lioncash
33bc59c55a
A64: Implement AESE
2018-02-03 23:11:46 +00:00
MerryMage
a7209dc2f7
IR: Add IR instruction NZCVFromPackedFlags
...
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
2018-02-03 13:41:36 +00:00
MerryMage
6d9adb668e
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
2018-02-02 21:10:30 +00:00
MerryMage
cc40b83ed0
IR: Implement VectorSetElement{8,16,32,64}
2018-02-02 21:00:12 +00:00
Lioncash
b608979be9
A64: Implement AESIMC and AESMC
2018-02-02 17:35:16 +00:00
Lioncash
7fb386aa1c
A64: Implement CRC32
2018-01-29 17:06:17 +00:00
MerryMage
14910e53d3
A32: Add ExceptionRaised IR instruction and use it
2018-01-28 12:59:52 +00:00
Lioncash
0216cbd2a5
A64: Implement CRC32C
2018-01-28 12:20:56 +00:00
Lioncash
dbddb4858a
A64: Implement EXTR
2018-01-26 22:07:48 +00:00
MerryMage
0c1c82a937
IR: Implement IR instructions A64{Get,Set}S
2018-01-26 18:38:30 +00:00
MerryMage
f7e8a2259a
IR: Implement IR instructions VectorEqual{8,16,32,64,128}
2018-01-26 01:52:06 +00:00
Fernando Sahmkow
5ffd11d140
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions ( #142 )
2018-01-26 00:57:56 +00:00
MerryMage
314e020992
IR: Add IR instruction VectorZeroUpper
2018-01-24 17:11:13 +00:00
FernandoS27
d1664096f5
Implemented SDIV and UDIV instructions
2018-01-24 17:09:00 +00:00
MerryMage
d6589fe3ee
IR: Add IR instructions A64Memory{Read,Write}128
...
This implementation only works on macOS and Linux.
2018-01-24 16:18:58 +00:00
MerryMage
5421c90216
IR: Add IR instruction VectorGetElement{8,16,32,64}
2018-01-24 16:18:58 +00:00
MerryMage
3932d6d695
IR: Add IR instruction ZeroExtendToQuad
2018-01-24 16:18:58 +00:00
MerryMage
6f1c44e311
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
2018-01-24 12:01:26 +00:00
MerryMage
dfcbe5bd2f
IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
2018-01-23 17:46:28 +00:00
Lioncash
585e77d20e
opcodes: Add 64-bit CountLeadingZeroes opcode
2018-01-23 11:55:09 +00:00
MerryMage
a6d17e6bb0
A64: Implement AND (vector)
2018-01-21 18:27:06 +00:00
MerryMage
d333b5dcee
A64: Implement ADD (vector, vector)
2018-01-21 17:56:27 +00:00
MerryMage
9fc1570788
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128
...
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
2018-01-19 01:09:46 +00:00
MerryMage
2f84137f5b
IR: Implement Conditional Select
2018-01-18 11:36:52 +00:00
MerryMage
9ab130490b
A64: Add ExceptionRaised IR instruction
...
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2018-01-13 18:06:06 +00:00
MerryMage
16e50ca0db
A32: Implement load stores (immediate)
2018-01-10 01:30:30 +00:00
MerryMage
f19f014a42
A64: Implement SVC
2018-01-09 18:57:07 +00:00
MerryMage
305456b407
A64: Implement compare and branch
2018-01-09 18:57:06 +00:00
MerryMage
c4abd1fda1
A64: Implement branch (register)
2018-01-09 18:57:06 +00:00
MerryMage
f3e763a667
A64: Implement logical
2018-01-09 18:57:06 +00:00
MerryMage
8a8dcad250
A64: Implement addsub instructions
2018-01-09 18:57:06 +00:00
MerryMage
1431cedcaa
A64: Implement ADD_shifted
2018-01-09 18:57:06 +00:00
MerryMage
b88b7ecbbf
IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg
2018-01-09 18:20:57 +00:00
MerryMage
42c83fadce
IR: Split off A32 specific opcodes
2018-01-09 18:20:57 +00:00
MerryMage
976a098bf6
jit_state: Split off CPSR.NZCV
2017-12-12 14:24:07 +00:00
MerryMage
311b6609aa
Implement IR instruction PackedSelect, reimplement SEL
2017-11-25 16:33:48 +00:00
MerryMage
05e97058c3
parallel: Add and Subtract with Exchange improvements
...
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
2017-03-24 15:56:24 +00:00
MerryMage
bbeea72eba
ir_opt: Remove redundant shift instructions
2017-02-26 15:28:14 +00:00
MerryMage
48693eb6ff
Implement coprocessor-related microinstructions
...
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
2017-01-08 14:56:06 +00:00
MerryMage
1efd3a764d
IR: Remove unused microinstructions NegateLowWord and NegateHighWord
2017-01-05 20:16:39 +00:00
FernandoS27
d5610eb26c
Implement UHASX, UHSAX, SHASX and SHSAX ( #75 )
2016-12-28 21:32:22 +00:00
Fernando Sahmkow
677f62dd6f
Implement SHSUB8 and SHSUB16 ( #74 )
...
* Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
2016-12-22 12:02:24 +00:00
MerryMage
6a269a6ebd
IR: Add microinstructions UnsignedSaturation and SignedSaturation
2016-12-21 19:51:25 +00:00
FernandoS27
8919265d2c
Implement SADD8, SADD16, SSUB8, SSUB16, USUB16
2016-12-20 21:52:38 +00:00
FernandoS27
3f6ecfe245
Implemented USAD8 and USADA8
2016-12-20 21:52:38 +00:00
MerryMage
96e46ba6b5
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:34:29 +00:00
MerryMage
52e1445f43
Implement USUB8
2016-12-05 00:29:15 +00:00
MerryMage
5c1aab1666
Implement CLZ
...
Includes tests
2016-12-04 22:56:33 +00:00
