Lioncash
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ef1e69a1e3
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A64: Implement SSHL (vector)
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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21974ee57e
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backend_x64/ir: Amend generic LogicalVShift() template to also handle signed variants
Also adds IR opcodes to dispatch said variants
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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ba1cc6366d
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A64: Implement RSUBHN/RSUBHN2
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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e41640fe33
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A64: Implement RADDHN/RADDHN2
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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b595a68ffa
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A64: Implement CMTST (vector)
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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48c7f8630c
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A64: Implement ADDHN{2} and SUBHN{2}
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2020-04-22 20:46:17 +01:00 |
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MerryMage
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5c47f03888
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A64: Implement FMUL (vector)
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2020-04-22 20:46:15 +01:00 |
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Lioncash
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a6e264c2dd
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A64: Implement UABA
Now that we have unsigned absolute difference capabilities, we can just use this to
append onto the result via a vector add.
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2020-04-22 20:46:15 +01:00 |
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Lioncash
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c2e7364d3e
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A64: Implement UABD
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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49cc6d7fad
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A64: Implement FDIV (vector)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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147284427b
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A64: Implement USHL
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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ccf7df057b
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simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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d5af052f06
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A64: Implement CMGE (register)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9d85991906
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A64: Implement CMHI, CMHS
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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0df6725f73
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A64: Implement SMAX, SMIN, UMAX, UMIN
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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adb7f5f86f
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A64: Implement CMGT (register)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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aed4fd3ec3
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A64: Implement FADD (vector), vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f1cb5581c9
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A64: Implement FSUB (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1dd2b33b87
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A64: Implement MLS (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5eac3abf52
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A64: Implement MLA (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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3afd2fcbad
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A64: Implement MUL (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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faeb77e8c4
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A64: Implement SUB (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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d3a4e1efe2
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IR: Vector instructions now take esize argument in emitter
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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15e8231f24
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opcodes: Sort vector IR opcodes alphabetically
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2020-04-22 20:46:13 +01:00 |
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FernandoS27
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15871910af
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Implemented BSL, BIC, BIT and BIF vector instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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2a0850c068
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A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7b33772ac6
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A64: Implement BIC (vector, register)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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67443efb62
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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7abd673a49
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A64: Zero upper 64 bits in ORN if using the 64-bit variant
Resolves a TODO
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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75756137c6
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A64: Implement CMEQ (register, vector)
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2020-04-22 20:44:38 +01:00 |
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Fernando Sahmkow
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e0c12ec2ad
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A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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b8e26bfdc3
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A64: Implement ADDP (vector)
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2020-04-22 20:42:46 +01:00 |
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MerryMage
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f81d0a2536
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A64: Implement AND (vector)
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2020-04-22 20:42:46 +01:00 |
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MerryMage
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a63fc6c89b
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A64: Implement ADD (vector, vector)
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2020-04-22 20:42:46 +01:00 |
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