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95a83543f2
intrusive_list: Get rid of unnecessary static_casts
2016-08-18 10:14:29 -04:00
67509935f6
intrusive_list: Eliminate need for separate const iterator construct
2016-08-18 10:02:36 -04:00
b8cf43c43e
translate_arm/data_processing: Rd == R15 is unpredictable for rsr instructions
2016-08-18 18:23:05 +01:00
efc8d2f772
arm_translator: NV conditional is obsolete
2016-08-18 18:21:48 +01:00
5f7d940fde
disassemble_arm: Partially implement coprocessor and hint instructions
2016-08-18 18:21:16 +01:00
36a916a766
decoder/arm: Correct NOP decoder
2016-08-18 18:20:29 +01:00
e9e7ac6e65
decoder/arm: Correct PLD decoder for v6K
2016-08-18 18:19:34 +01:00
269160ef0d
emit_x64: Clear RSB-related caches when ClearCache() is called
2016-08-18 18:18:44 +01:00
1a3f3ac435
emit_x64: Correct behaviour of PackedOperation for immediate argument
2016-08-18 18:17:17 +01:00
b2de47954b
EmitX64: Emit correct cycle count on cond failure
2016-08-18 18:16:18 +01:00
841098a0bc
ir: separate components out a little more
2016-08-17 10:53:36 -04:00
9690d1423d
intrusive_list: explicitly default relevant constructors
2016-08-16 23:50:17 -04:00
cbd99e4367
jitstate: Use std::array's fill() in ResetRSB
2016-08-16 13:47:31 -04:00
74ee92ee38
jitstate: const correctness
2016-08-16 13:41:16 -04:00
9ed9f4c565
mp: Generalize function information retrieval
2016-08-16 12:40:04 -04:00
439619c827
reg_alloc: Make GetRegLoc return by const reference
2016-08-16 14:52:46 -04:00
0ebb572e2d
Optimization: Make RSB a ring buffer instead of a stack
2016-08-15 15:48:22 +01:00
7d7ac0af71
Optimization: Make SVC use RSB
2016-08-15 15:02:08 +01:00
6c45619aa1
Optimization: Implement terminal LinkBlockFast
2016-08-15 14:33:17 +01:00
624e84fa09
Optimization: Tweak RSB
2016-08-15 14:08:06 +01:00
070298b948
Optimization: bugfix! Return Stack Buffer location hash calculation was incorrect
2016-08-15 13:21:58 +01:00
e164ede4dc
TranslateArm: Implement MRS, MSR (imm), MSR (reg)
2016-08-14 19:39:16 +01:00
30f3d869cc
TranslateArm: Implement VPUSH and VPOP.
2016-08-13 01:51:55 -04:00
9c82a12f8f
ir_opt: Update VerificationPass to current IR
2016-08-13 18:39:49 +01:00
8fc21f481a
RegAlloc: Handle case when def is unused
2016-08-13 01:55:03 +01:00
d43d97b990
EmitX64/EmitPushRSB: Assert that patch location is of correct size
2016-08-13 00:52:31 +01:00
960d14d18e
Optimization: Implement Return Stack Buffer
2016-08-13 00:10:23 +01:00
8e68e6fdd9
TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
2016-08-12 13:42:16 -04:00
4b09c0d032
TranslateArm: Implement QADD8 and UQADD8.
2016-08-12 13:26:14 -04:00
127fbe99cb
TranslateArm: Implement QSUB8.
2016-08-12 13:18:38 -04:00
86fe29c6d2
TranslateArm: Implement UQSUB8.
2016-08-12 11:53:16 -04:00
1029fd27ce
Update documentation (2016-08-12)
2016-08-12 18:17:31 +01:00
3808938c98
Fix SETEND
2016-08-11 19:15:58 +01:00
218980cf69
load_store: Implement LDRSB and LDRSH.
2016-08-11 17:18:20 +01:00
0e5593ba62
TranslateArm: Implement SETEND
2016-08-11 17:15:33 +01:00
8964b38cf9
IR/DumpBlock: Print references to ExtRegs
2016-08-11 17:15:02 +01:00
b4c586d5ef
TranslateArm: VSTR: Correct behaviour in big-endian mode
2016-08-10 16:43:37 +01:00
945498a16a
DisassemblerArm: Disassemble SETEND
2016-08-10 16:15:07 +01:00
8e8db6e137
TranslateArm: Implement VSTR.
2016-08-10 15:01:23 +01:00
df39308e03
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
d921390928
TranslateArm: Add santity check to see if we've emitted a terminal instruction
2016-08-09 22:47:41 +01:00
2eec43178a
IR: Opaque can be of any type
2016-08-09 22:46:44 +01:00
29d30bf931
Interface: Added Jit::Reset to reset CPU state
2016-08-09 22:45:54 +01:00
82f42d065f
DisassemblerArm: Implemented disassembly of STR*/LDR* instructions
2016-08-09 22:44:42 +01:00
d0d51ba346
TranslateArm: Implement STM, STMDA, STMDB, STMIB
2016-08-08 22:49:11 +01:00
5d26899ac9
Add simplified LogicalShiftRight64 IR opcode
2016-08-07 14:23:33 +01:00
ccb2aa96a5
Add support for the APSR.Q flag
2016-08-06 22:04:52 +01:00
11e0688e5f
Fix build on case-sensitive file systems
2016-08-08 10:11:54 +01:00
85549d7ae2
TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB
2016-08-08 22:21:10 +01:00
46e4864707
ArmTypes: Add RegListToString and reorganise
2016-08-08 22:20:28 +01:00
975f011fc0
BackendX64/RegAlloc: Do not allocate RSP for guest use
2016-08-08 16:01:07 +01:00
abd113f160
EmitX64: Renamed patch_jmp_locations to patch_jg_locations
2016-08-08 15:56:07 +01:00
52fa998e6b
EmitX64: EmitTerminalLinkBlock: Fix behaviour when setting T and E flags
2016-08-07 22:47:43 +01:00
04c1a0d2de
EmitX64: Switch MXCSR when switching to interpreter
2016-08-07 22:47:17 +01:00
edb236ab07
Correct implementation of thumb16_SVC and arm_SVC
2016-08-07 22:19:39 +01:00
a32063fa60
EmitX64: Implement block linking
2016-08-07 22:11:39 +01:00
b3bb1d5048
Tests: Tidy up ARM fuzz tests
2016-08-07 21:55:38 +01:00
328422b740
RegAlloc: HostCall flushes all XMM regsiters
2016-08-07 21:02:16 +01:00
4dcd1d1859
Arm: BLX is UNPREDICTABLE when Rm is PC
2016-08-07 20:50:33 +01:00
1af5bef32c
TranslateArm: Implement BLX (imm), BLX (reg) and BXJ
2016-08-07 20:19:37 +01:00
939bb5c0cb
TranslateArm: Implement NOP
2016-08-07 20:08:31 +01:00
e48df9d8fd
TranslateArm: Implement Hint instructions as NOPs
2016-08-07 20:04:48 +01:00
3a465ba4a8
VFP: Implement VLDR
2016-08-07 19:59:35 +01:00
a2c2db277b
VFP: Implement VMOV (all variants)
2016-08-07 19:25:12 +01:00
aba705f6b9
BackendX64: Merge Routines into BlockOfCode
2016-08-07 18:08:48 +01:00
0f412247ed
VFP: Implement VSQRT
2016-08-07 12:19:07 +01:00
cd8e7c0504
VFP: Implement VNEG
2016-08-07 12:04:21 +01:00
da33af5abe
VFP: Implement VMLA, VMLS, VNMLA, VNMLS
2016-08-07 11:38:30 +01:00
3f1345a1a5
VFP: Implement VNMUL, VDIV
2016-08-07 10:56:12 +01:00
12e7f2c359
VFP: Implement VMUL
2016-08-07 10:21:14 +01:00
97b5fa173f
VFP: Implement VSUB
2016-08-07 01:41:25 +01:00
ce6b5f8210
VFP: Implement VABS
2016-08-07 01:27:18 +01:00
f88b1b4c2e
FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask
2016-08-07 00:40:29 +01:00
c35f06470f
VFP: Interpret VFP instructions when FPSCR.Len or FPSCR.Stride != 1
2016-08-06 23:01:18 +01:00
94b99f5949
Common: Add an intrusive list implementation; remove use of boost::intrusive::list.
2016-08-06 22:23:01 +01:00
9264e2e04c
Use XOR when loading a zero immediate
2016-08-06 21:04:13 +01:00
55204a80d0
Implement SMMLA, SMMLS, SMMUL
2016-08-06 12:10:43 +01:00
846d07d7b5
Add Sub64 opcode
2016-08-06 06:09:47 +01:00
b9f4f1ed0f
Add carry support to MostSignificantWord
2016-08-06 21:03:57 +01:00
01aebcb385
Remove *MulHi wrappers
2016-08-06 05:21:29 +01:00
5e047107a0
Disassemble more instructions
2016-08-06 05:18:29 +01:00
f99cb613cf
Disassemble packs and more multiplies
2016-08-05 02:40:44 +01:00
81d9d4b012
Add Subv's sign/zero extension tests
2016-08-05 02:35:27 +01:00
a281fcc744
Fix printf
2016-08-06 21:16:29 +01:00
7915f97d98
TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning)
2016-08-06 20:42:06 +01:00
4d127c19dd
Common: Add a memory pool implementation, remove use of boost::pool
2016-08-06 20:41:00 +01:00
411e804b0d
Interface: Forward declare Arm::LocationDescriptor
2016-08-06 19:59:09 +01:00
9ab7626374
Tests/VFP: Add tests for VADD.F32
2016-08-06 17:31:01 +01:00
4b31ea25a7
VFP: Implement VADD.{F32,F64}
2016-08-06 17:21:29 +01:00
8ff414ee0e
Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top.
2016-08-06 17:17:58 +01:00
94d5738f62
BackendX64/Routines: Add floating-point constants
2016-08-06 17:12:40 +01:00
8754728a82
BackendX64/RegAlloc: Corrected code emitted by EmitMove for XMM->Spill case
2016-08-06 17:11:58 +01:00
8cc4fe8a10
BackendX64/RegAlloc: HostLocToX64 now handles XMM registers properly
2016-08-06 17:11:22 +01:00
cd1eef2801
Merged in bunnei/dynarmic/load_store (pull request #9 )
2016-08-06 14:22:45 +01:00
2448d52394
load_store: Use correct types for LDR/STR.
2016-08-05 20:51:32 -04:00
8c2300d477
arm: Implement LDRD reg/imm instructions.
2016-08-04 23:36:58 -04:00
72608b7af6
arm: Handle Cond::NV (some 3DS games use this despite being obsolete).
2016-08-04 23:14:15 -04:00
ec3a98cf95
arm: Implement LDRH reg/imm instructions.
2016-08-04 23:12:45 -04:00
192a0fba7a
arm: Implement LDRB reg/imm instructions.
2016-08-04 23:12:11 -04:00
dfb318f208
arm: Implement STRD reg/imm instructions.
2016-08-04 22:47:27 -04:00
Lioncash
MerryMage
bunnei
Tillmann Karras