Several issues: 1. Several terminal instructions did not stop at the end of a single-step block 2. x64 backend for the A32 frontend sometimes polluted upper_location_descriptor with the single-stepping flag We also introduce the enable_optimizations parameter to the A32 frontend.
144 lines
6.0 KiB
C++
144 lines
6.0 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#pragma once
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#include <array>
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#include <cstddef>
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#include <cstdint>
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#include <memory>
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namespace Dynarmic {
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namespace A32 {
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using VAddr = std::uint32_t;
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class Coprocessor;
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enum class Exception {
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/// An UndefinedFault occured due to executing instruction with an unallocated encoding
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UndefinedInstruction,
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/// An unpredictable instruction is to be executed. Implementation-defined behaviour should now happen.
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/// This behaviour is up to the user of this library to define.
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UnpredictableInstruction,
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/// A SEV instruction was executed. The event register of all PEs should be set. (Hint instruction.)
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SendEvent,
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/// A SEVL instruction was executed. The event register of the current PE should be set. (Hint instruction.)
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SendEventLocal,
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/// A WFI instruction was executed. You may now enter a low-power state. (Hint instruction.)
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WaitForInterrupt,
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/// A WFE instruction was executed. You may now enter a low-power state if the event register is clear. (Hint instruction.)
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WaitForEvent,
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/// A YIELD instruction was executed. (Hint instruction.)
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Yield,
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/// A BKPT instruction was executed.
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Breakpoint,
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/// A PLD instruction was executed. (Hint instruction.)
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PreloadData,
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/// A PLDW instruction was executed. (Hint instruction.)
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PreloadDataWithIntentToWrite,
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};
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/// These function pointers may be inserted into compiled code.
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struct UserCallbacks {
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virtual ~UserCallbacks() = default;
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// All reads through this callback are 4-byte aligned.
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// Memory must be interpreted as little endian.
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virtual std::uint32_t MemoryReadCode(VAddr vaddr) { return MemoryRead32(vaddr); }
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// Reads through these callbacks may not be aligned.
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// Memory must be interpreted as if ENDIANSTATE == 0, endianness will be corrected by the JIT.
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virtual std::uint8_t MemoryRead8(VAddr vaddr) = 0;
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virtual std::uint16_t MemoryRead16(VAddr vaddr) = 0;
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virtual std::uint32_t MemoryRead32(VAddr vaddr) = 0;
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virtual std::uint64_t MemoryRead64(VAddr vaddr) = 0;
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// Writes through these callbacks may not be aligned.
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virtual void MemoryWrite8(VAddr vaddr, std::uint8_t value) = 0;
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virtual void MemoryWrite16(VAddr vaddr, std::uint16_t value) = 0;
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virtual void MemoryWrite32(VAddr vaddr, std::uint32_t value) = 0;
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virtual void MemoryWrite64(VAddr vaddr, std::uint64_t value) = 0;
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// If this callback returns true, the JIT will assume MemoryRead* callbacks will always
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// return the same value at any point in time for this vaddr. The JIT may use this information
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// in optimizations.
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// A conservative implementation that always returns false is safe.
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virtual bool IsReadOnlyMemory(VAddr /* vaddr */) { return false; }
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/// The interpreter must execute exactly num_instructions starting from PC.
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virtual void InterpreterFallback(VAddr pc, size_t num_instructions) = 0;
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// This callback is called whenever a SVC instruction is executed.
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virtual void CallSVC(std::uint32_t swi) = 0;
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virtual void ExceptionRaised(VAddr pc, Exception exception) = 0;
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// Timing-related callbacks
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// ticks ticks have passed
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virtual void AddTicks(std::uint64_t ticks) = 0;
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// How many more ticks am I allowed to execute?
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virtual std::uint64_t GetTicksRemaining() = 0;
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};
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struct UserConfig {
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UserCallbacks* callbacks;
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/// When set to false, this disables all optimizations than can't otherwise be disabled
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/// by setting other configuration options. This includes:
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/// - IR optimizations
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/// - Block linking optimizations
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/// - RSB optimizations
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/// This is intended to be used for debugging.
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bool enable_optimizations = true;
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// Page Table
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// The page table is used for faster memory access. If an entry in the table is nullptr,
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// the JIT will fallback to calling the MemoryRead*/MemoryWrite* callbacks.
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static constexpr std::size_t PAGE_BITS = 12;
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static constexpr std::size_t NUM_PAGE_TABLE_ENTRIES = 1 << (32 - PAGE_BITS);
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std::array<std::uint8_t*, NUM_PAGE_TABLE_ENTRIES>* page_table = nullptr;
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/// Determines if the pointer in the page_table shall be offseted locally or globally.
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/// 'false' will access page_table[addr >> bits][addr & mask]
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/// 'true' will access page_table[addr >> bits][addr]
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/// Note: page_table[addr >> bits] will still be checked to verify active pages.
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/// So there might be wrongly faulted pages which maps to nullptr.
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/// This can be avoided by carefully allocating the memory region.
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bool absolute_offset_page_table = false;
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// Fastmem Pointer
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// This should point to the beginning of a 4GB address space which is in arranged just like
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// what you wish for emulated memory to be. If the host page faults on an address, the JIT
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// will fallback to calling the MemoryRead*/MemoryWrite* callbacks.
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void* fastmem_pointer = nullptr;
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/// Determines if instructions that pagefault should cause recompilation of that block
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/// with fastmem disabled.
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bool recompile_on_fastmem_failure = true;
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// Coprocessors
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std::array<std::shared_ptr<Coprocessor>, 16> coprocessors{};
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/// Hint instructions would cause ExceptionRaised to be called with the appropriate
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/// argument.
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bool hook_hint_instructions = false;
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/// This option relates to translation. Generally when we run into an unpredictable
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/// instruction the ExceptionRaised callback is called. If this is true, we define
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/// definite behaviour for some unpredictable instructions.
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bool define_unpredictable_behaviour = false;
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/// This enables the fast dispatcher.
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bool enable_fast_dispatch = true;
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/// This option relates to the CPSR.E flag. Enabling this option disables modification
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/// of CPSR.E by the emulated program, forcing it to 0.
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/// NOTE: Calling Jit::SetCpsr with CPSR.E=1 while this option is enabled may result
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/// in unusual behavior.
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bool always_little_endian = false;
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};
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} // namespace A32
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} // namespace Dynarmic
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