102 lines
3.4 KiB
C++
102 lines
3.4 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <limits>
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#include "backend/A64/block_of_code.h"
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#include "backend/A64/emit_a64.h"
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#include "common/assert.h"
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#include "common/bit_util.h"
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#include "common/common_types.h"
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#include "common/mp/integer.h"
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/microinstruction.h"
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#include "frontend/ir/opcodes.h"
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namespace Dynarmic::BackendA64 {
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namespace mp = Dynarmic::Common::mp;
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void EmitA64::EmitSignedSaturation(EmitContext& ctx, IR::Inst* inst) {
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const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const size_t N = args[1].GetImmediateU8();
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ASSERT(N >= 1 && N <= 32);
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if (N == 32) {
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if (overflow_inst) {
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const auto no_overflow = IR::Value(false);
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overflow_inst->ReplaceUsesWith(no_overflow);
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}
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ctx.reg_alloc.DefineValue(inst, args[0]);
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return;
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}
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const u32 mask = (1u << N) - 1;
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const u32 positive_saturated_value = (1u << (N - 1)) - 1;
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const u32 negative_saturated_value = 1u << (N - 1);
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const u32 sext_negative_satured_value = Common::SignExtend(N, negative_saturated_value);
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const ARM64Reg result = DecodeReg(ctx.reg_alloc.ScratchGpr());
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const ARM64Reg reg_a = DecodeReg(ctx.reg_alloc.UseGpr(args[0]));
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const ARM64Reg overflow = DecodeReg(ctx.reg_alloc.ScratchGpr());
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const ARM64Reg tmp = DecodeReg(ctx.reg_alloc.ScratchGpr());
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// overflow now contains a value between 0 and mask if it was originally between {negative,positive}_saturated_value.
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code.ADDI2R(overflow, reg_a, negative_saturated_value, overflow);
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// Put the appropriate saturated value in result
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code.MOVI2R(tmp, positive_saturated_value);
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code.CMP(reg_a, tmp);
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code.MOVI2R(result, sext_negative_satured_value);
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code.CSEL(result, tmp, result, CC_GT);
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// Do the saturation
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code.CMPI2R(overflow, mask, tmp);
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code.CSEL(result, reg_a, result, CC_LS);
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if (overflow_inst) {
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code.CSET(overflow, CC_HI);
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ctx.reg_alloc.DefineValue(overflow_inst, overflow);
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ctx.EraseInstruction(overflow_inst);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitUnsignedSaturation(EmitContext& ctx, IR::Inst* inst) {
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const auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const size_t N = args[1].GetImmediateU8();
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ASSERT(N <= 31);
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const u32 saturated_value = (1u << N) - 1;
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const ARM64Reg result = DecodeReg(ctx.reg_alloc.ScratchGpr());
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const ARM64Reg reg_a = DecodeReg(ctx.reg_alloc.UseGpr(args[0]));
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const ARM64Reg overflow = DecodeReg(ctx.reg_alloc.ScratchGpr());
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// Pseudocode: result = clamp(reg_a, 0, saturated_value);
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code.MOVI2R(result, saturated_value);
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code.CMP(reg_a, result);
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code.CSEL(result, WZR, result, CC_LE);
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code.CSEL(result, reg_a, result, CC_LS);
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if (overflow_inst) {
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code.CSET(overflow, CC_HI);
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ctx.reg_alloc.DefineValue(overflow_inst, overflow);
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ctx.EraseInstruction(overflow_inst);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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} // namespace Dynarmic::BackendA64
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