140 lines
4.9 KiB
C++
140 lines
4.9 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "translate_arm.h"
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namespace Dynarmic {
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namespace Arm {
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IR::Value ArmTranslatorVisitor::SignZeroExtendRor(Reg m, SignExtendRotation rotate) {
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IR::Value rotated, reg_m = ir.GetRegister(m);
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switch (rotate) {
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case SignExtendRotation::ROR_0:
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rotated = reg_m;
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break;
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case SignExtendRotation::ROR_8:
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rotated = ir.RotateRight(reg_m, ir.Imm8(8), ir.Imm1(0)).result;
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break;
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case SignExtendRotation::ROR_16:
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rotated = ir.RotateRight(reg_m, ir.Imm8(16), ir.Imm1(0)).result;
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break;
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case SignExtendRotation::ROR_24:
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rotated = ir.RotateRight(reg_m, ir.Imm8(24), ir.Imm1(0)).result;
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}
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return rotated;
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}
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bool ArmTranslatorVisitor::arm_SXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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if (d == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto rotated = SignZeroExtendRor(m, rotate);
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auto reg_n = ir.GetRegister(n);
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auto result = ir.Add(reg_n, ir.SignExtendByteToWord(ir.LeastSignificantByte(rotated)));
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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if (d == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto rotated = SignZeroExtendRor(m, rotate);
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auto reg_n = ir.GetRegister(n);
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auto result = ir.Add(reg_n, ir.SignExtendHalfToWord(ir.LeastSignificantHalf(rotated)));
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
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if (d == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto rotated = SignZeroExtendRor(m, rotate);
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auto result = ir.SignExtendByteToWord(ir.LeastSignificantByte(rotated));
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
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if (d == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto rotated = SignZeroExtendRor(m, rotate);
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auto result = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(rotated));
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_UXTAB(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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if (d == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto rotated = SignZeroExtendRor(m, rotate);
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auto reg_n = ir.GetRegister(n);
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auto result = ir.Add(reg_n, ir.ZeroExtendByteToWord(ir.LeastSignificantByte(rotated)));
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_UXTAB16(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UXTAH(Cond cond, Reg n, Reg d, SignExtendRotation rotate, Reg m) {
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if (d == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto rotated = SignZeroExtendRor(m, rotate);
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auto reg_n = ir.GetRegister(n);
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auto result = ir.Add(reg_n, ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(rotated)));
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_UXTB(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
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if (d == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto rotated = SignZeroExtendRor(m, rotate);
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auto result = ir.ZeroExtendByteToWord(ir.LeastSignificantByte(rotated));
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_UXTB16(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_UXTH(Cond cond, Reg d, SignExtendRotation rotate, Reg m) {
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if (d == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto rotated = SignZeroExtendRor(m, rotate);
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auto result = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(rotated));
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ir.SetRegister(d, result);
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}
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return true;
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}
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} // namespace Arm
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} // namespace Dynarmic
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