79 lines
2.1 KiB
C++
79 lines
2.1 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "translate_arm.h"
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#include "common/bit_util.h"
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namespace Dynarmic::A32 {
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bool ArmTranslatorVisitor::arm_CPS() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_MRS(Cond cond, Reg d) {
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if (d == Reg::PC)
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return UnpredictableInstruction();
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// MRS <Rd>, APSR
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if (ConditionPassed(cond)) {
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ir.SetRegister(d, ir.GetCpsr());
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_MSR_imm(Cond cond, int mask, int rotate, Imm8 imm8) {
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bool write_nzcvq = Common::Bit<1>(mask);
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bool write_g = Common::Bit<0>(mask);
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u32 imm32 = ArmExpandImm(rotate, imm8);
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ASSERT_MSG(write_nzcvq || write_g, "Decode error");
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// MSR <spec_reg>, #<imm32>
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if (ConditionPassed(cond)) {
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if (write_nzcvq) {
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ir.SetCpsrNZCVQ(ir.Imm32(imm32 & 0xF8000000));
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}
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if (write_g) {
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ir.SetGEFlagsCompressed(ir.Imm32(imm32 & 0x000F0000));
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}
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_MSR_reg(Cond cond, int mask, Reg n) {
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bool write_nzcvq = Common::Bit<1>(mask);
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bool write_g = Common::Bit<0>(mask);
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if (!write_nzcvq && !write_g)
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return UnpredictableInstruction();
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if (n == Reg::PC)
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return UnpredictableInstruction();
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// MSR <spec_reg>, #<imm32>
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if (ConditionPassed(cond)) {
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auto value = ir.GetRegister(n);
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if (write_nzcvq){
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ir.SetCpsrNZCVQ(ir.And(value, ir.Imm32(0xF8000000)));
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}
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if (write_g){
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ir.SetGEFlagsCompressed(ir.And(value, ir.Imm32(0x000F0000)));
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}
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_RFE() {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_SETEND(bool E) {
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// SETEND {BE,LE}
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ir.SetTerm(IR::Term::LinkBlock{ir.current_location.AdvancePC(4).SetEFlag(E)});
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return false;
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}
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bool ArmTranslatorVisitor::arm_SRS() {
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return InterpretThisInstruction();
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}
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} // namespace Dynarmic::A32
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