435 lines
18 KiB
C++
435 lines
18 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "translate_arm.h"
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namespace Dynarmic {
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namespace Arm {
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// Multiply (Normal) instructions
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bool ArmTranslatorVisitor::arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC || a == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto result = ir.Add(ir.Mul(ir.GetRegister(n), ir.GetRegister(m)), ir.GetRegister(a));
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ir.SetRegister(d, result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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}
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto result = ir.Mul(ir.GetRegister(n), ir.GetRegister(m));
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ir.SetRegister(d, result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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}
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}
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return true;
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}
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// Multiply (Long) instructions
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bool ArmTranslatorVisitor::arm_SMLAL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) {
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (dLo == dHi)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n64 = ir.SignExtendWordToLong(ir.GetRegister(n));
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auto m64 = ir.SignExtendWordToLong(ir.GetRegister(m));
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auto product = ir.Mul64(n64, m64);
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auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
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auto result = ir.Add64(product, addend);
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auto lo = ir.LeastSignificantWord(result);
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auto hi = ir.MostSignificantWord(result).result;
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ir.SetRegister(dLo, lo);
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ir.SetRegister(dHi, hi);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(hi));
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ir.SetZFlag(ir.IsZero64(result));
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}
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMULL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) {
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (dLo == dHi)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n64 = ir.SignExtendWordToLong(ir.GetRegister(n));
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auto m64 = ir.SignExtendWordToLong(ir.GetRegister(m));
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auto result = ir.Mul64(n64, m64);
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auto lo = ir.LeastSignificantWord(result);
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auto hi = ir.MostSignificantWord(result).result;
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ir.SetRegister(dLo, lo);
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ir.SetRegister(dHi, hi);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(hi));
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ir.SetZFlag(ir.IsZero64(result));
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}
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_UMAAL(Cond cond, Reg dHi, Reg dLo, Reg m, Reg n) {
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (dLo == dHi)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto lo64 = ir.ZeroExtendWordToLong(ir.GetRegister(dLo));
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auto hi64 = ir.ZeroExtendWordToLong(ir.GetRegister(dHi));
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auto n64 = ir.ZeroExtendWordToLong(ir.GetRegister(n));
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auto m64 = ir.ZeroExtendWordToLong(ir.GetRegister(m));
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auto result = ir.Add64(ir.Add64(ir.Mul64(n64, m64), hi64), lo64);
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ir.SetRegister(dLo, ir.LeastSignificantWord(result));
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ir.SetRegister(dHi, ir.MostSignificantWord(result).result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_UMLAL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) {
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (dLo == dHi)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
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auto n64 = ir.ZeroExtendWordToLong(ir.GetRegister(n));
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auto m64 = ir.ZeroExtendWordToLong(ir.GetRegister(m));
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auto result = ir.Add64(ir.Mul64(n64, m64), addend);
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auto lo = ir.LeastSignificantWord(result);
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auto hi = ir.MostSignificantWord(result).result;
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ir.SetRegister(dLo, lo);
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ir.SetRegister(dHi, hi);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(hi));
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ir.SetZFlag(ir.IsZero64(result));
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}
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_UMULL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m, Reg n) {
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (dLo == dHi)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n64 = ir.ZeroExtendWordToLong(ir.GetRegister(n));
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auto m64 = ir.ZeroExtendWordToLong(ir.GetRegister(m));
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auto result = ir.Mul64(n64, m64);
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auto lo = ir.LeastSignificantWord(result);
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auto hi = ir.MostSignificantWord(result).result;
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ir.SetRegister(dLo, lo);
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ir.SetRegister(dHi, hi);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(hi));
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ir.SetZFlag(ir.IsZero64(result));
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}
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}
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return true;
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}
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// Multiply (Halfword) instructions
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bool ArmTranslatorVisitor::arm_SMLALxy(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, bool N, Reg n) {
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (dLo == dHi)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto product = ir.SignExtendWordToLong(ir.Mul(n16, m16));
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auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
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auto result = ir.Add64(product, addend);
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ir.SetRegister(dLo, ir.LeastSignificantWord(result));
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ir.SetRegister(dHi, ir.MostSignificantWord(result).result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMLAxy(Cond cond, Reg d, Reg a, Reg m, bool M, bool N, Reg n) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC || a == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto product = ir.Mul(n16, m16);
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auto result_overflow = ir.AddWithCarry(product, ir.GetRegister(a), ir.Imm1(0));
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ir.SetRegister(d, result_overflow.result);
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ir.OrQFlag(result_overflow.overflow);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMULxy(Cond cond, Reg d, Reg m, bool M, bool N, Reg n) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto result = ir.Mul(n16, m16);
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ir.SetRegister(d, result);
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}
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return true;
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}
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// Multiply (word by halfword) instructions
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bool ArmTranslatorVisitor::arm_SMLAWy(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC || a == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.SignExtendWordToLong(ir.GetRegister(n));
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auto m32 = ir.GetRegister(m);
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if (M)
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m32 = ir.LogicalShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m16 = ir.LeastSignificantHalf(m32);
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m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(m16));
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auto product = ir.LeastSignificantWord(ir.LogicalShiftRight64(ir.Mul64(n32, m16), ir.Imm8(16)));
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auto result_overflow = ir.AddWithCarry(product, ir.GetRegister(a), ir.Imm1(0));
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ir.SetRegister(d, result_overflow.result);
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ir.OrQFlag(result_overflow.overflow);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMULWy(Cond cond, Reg d, Reg m, bool M, Reg n) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.SignExtendWordToLong(ir.GetRegister(n));
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auto m32 = ir.GetRegister(m);
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if (M)
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m32 = ir.LogicalShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m16 = ir.LeastSignificantHalf(m32);
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m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(m16));
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auto result = ir.LogicalShiftRight64(ir.Mul64(n32, m16), ir.Imm8(16));
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ir.SetRegister(d, ir.LeastSignificantWord(result));
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}
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return true;
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}
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// Multiply (Most significant word) instructions
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bool ArmTranslatorVisitor::arm_SMMLA(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC /* no check for a */)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n64 = ir.SignExtendWordToLong(ir.GetRegister(n));
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auto m64 = ir.SignExtendWordToLong(ir.GetRegister(m));
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auto a64 = ir.Pack2x32To1x64(ir.Imm32(0), ir.GetRegister(a));
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auto temp = ir.Add64(a64, ir.Mul64(n64, m64));
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auto result_carry = ir.MostSignificantWord(temp);
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auto result = result_carry.result;
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if (R)
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result = ir.AddWithCarry(result, ir.Imm32(0), result_carry.carry).result;
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMMLS(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC || a == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n64 = ir.SignExtendWordToLong(ir.GetRegister(n));
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auto m64 = ir.SignExtendWordToLong(ir.GetRegister(m));
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auto a64 = ir.Pack2x32To1x64(ir.Imm32(0), ir.GetRegister(a));
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auto temp = ir.Sub64(a64, ir.Mul64(n64, m64));
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auto result_carry = ir.MostSignificantWord(temp);
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auto result = result_carry.result;
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if (R)
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result = ir.AddWithCarry(result, ir.Imm32(0), result_carry.carry).result;
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMMUL(Cond cond, Reg d, Reg m, bool R, Reg n) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n64 = ir.SignExtendWordToLong(ir.GetRegister(n));
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auto m64 = ir.SignExtendWordToLong(ir.GetRegister(m));
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auto product = ir.Mul64(n64, m64);
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auto result_carry = ir.MostSignificantWord(product);
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auto result = result_carry.result;
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if (R)
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result = ir.AddWithCarry(result, ir.Imm32(0), result_carry.carry).result;
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ir.SetRegister(d, result);
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}
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return true;
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}
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// Multiply (Dual) instructions
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bool ArmTranslatorVisitor::arm_SMLAD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) {
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if (a == Reg::PC)
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return arm_SMUAD(cond, d, m, M, n);
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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if (M)
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std::swap(m_lo, m_hi);
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auto product_lo = ir.Mul(n_lo, m_lo);
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auto product_hi = ir.Mul(n_hi, m_hi);
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auto addend = ir.GetRegister(a);
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auto result_overflow = ir.AddWithCarry(product_lo, product_hi, ir.Imm1(0));
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ir.OrQFlag(result_overflow.overflow);
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result_overflow = ir.AddWithCarry(result_overflow.result, addend, ir.Imm1(0));
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ir.SetRegister(d, result_overflow.result);
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ir.OrQFlag(result_overflow.overflow);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMLALD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n) {
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (dLo == dHi)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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if (M)
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std::swap(m_lo, m_hi);
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auto product_lo = ir.SignExtendWordToLong(ir.Mul(n_lo, m_lo));
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auto product_hi = ir.SignExtendWordToLong(ir.Mul(n_hi, m_hi));
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auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
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auto result = ir.Add64(ir.Add64(product_lo, product_hi), addend);
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ir.SetRegister(dLo, ir.LeastSignificantWord(result));
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ir.SetRegister(dHi, ir.MostSignificantWord(result).result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMLSD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) {
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if (a == Reg::PC)
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return arm_SMUSD(cond, d, m, M, n);
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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if (M)
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std::swap(m_lo, m_hi);
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auto product_lo = ir.Mul(n_lo, m_lo);
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auto product_hi = ir.Mul(n_hi, m_hi);
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auto addend = ir.GetRegister(a);
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auto result_overflow = ir.AddWithCarry(ir.Sub(product_lo, product_hi), addend, ir.Imm1(0));
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ir.SetRegister(d, result_overflow.result);
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ir.OrQFlag(result_overflow.overflow);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMLSLD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n) {
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (dLo == dHi)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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if (M)
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std::swap(m_lo, m_hi);
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auto product_lo = ir.SignExtendWordToLong(ir.Mul(n_lo, m_lo));
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auto product_hi = ir.SignExtendWordToLong(ir.Mul(n_hi, m_hi));
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auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
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auto result = ir.Add64(ir.Sub64(product_lo, product_hi), addend);
|
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ir.SetRegister(dLo, ir.LeastSignificantWord(result));
|
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ir.SetRegister(dHi, ir.MostSignificantWord(result).result);
|
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}
|
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return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::arm_SMUAD(Cond cond, Reg d, Reg m, bool M, Reg n) {
|
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
|
|
return UnpredictableInstruction();
|
|
if (ConditionPassed(cond)) {
|
|
auto n32 = ir.GetRegister(n);
|
|
auto m32 = ir.GetRegister(m);
|
|
auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
|
|
auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
|
|
auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
|
|
auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
|
|
if (M)
|
|
std::swap(m_lo, m_hi);
|
|
auto product_lo = ir.Mul(n_lo, m_lo);
|
|
auto product_hi = ir.Mul(n_hi, m_hi);
|
|
auto result_overflow = ir.AddWithCarry(product_lo, product_hi, ir.Imm1(0));
|
|
ir.SetRegister(d, result_overflow.result);
|
|
ir.OrQFlag(result_overflow.overflow);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmTranslatorVisitor::arm_SMUSD(Cond cond, Reg d, Reg m, bool M, Reg n) {
|
|
if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
|
|
return UnpredictableInstruction();
|
|
if (ConditionPassed(cond)) {
|
|
auto n32 = ir.GetRegister(n);
|
|
auto m32 = ir.GetRegister(m);
|
|
auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
|
|
auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
|
|
auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
|
|
auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
|
|
if (M)
|
|
std::swap(m_lo, m_hi);
|
|
auto product_lo = ir.Mul(n_lo, m_lo);
|
|
auto product_hi = ir.Mul(n_hi, m_hi);
|
|
auto result = ir.Sub(product_lo, product_hi);
|
|
ir.SetRegister(d, result);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
} // namespace Arm
|
|
} // namespace Dynarmic
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