From c97efcb978f7093cda530bd5b403eef04e779e4c Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 23 Mar 2019 13:21:55 -0400 Subject: [PATCH 1/5] frontend/ir_emitter: Add half-precision variant of FPNeg --- src/backend/x64/emit_x64_floating_point.cpp | 15 +++++++++++++-- src/frontend/ir/ir_emitter.cpp | 12 +++++++++--- src/frontend/ir/ir_emitter.h | 2 +- src/frontend/ir/opcodes.inc | 1 + 4 files changed, 24 insertions(+), 6 deletions(-) diff --git a/src/backend/x64/emit_x64_floating_point.cpp b/src/backend/x64/emit_x64_floating_point.cpp index 028c281d..b06a9eeb 100644 --- a/src/backend/x64/emit_x64_floating_point.cpp +++ b/src/backend/x64/emit_x64_floating_point.cpp @@ -38,6 +38,8 @@ namespace { const Xbyak::Reg64 INVALID_REG = Xbyak::Reg64(-1); +constexpr u64 f16_negative_zero = 0x8000; + constexpr u64 f32_negative_zero = 0x80000000u; constexpr u64 f32_nan = 0x7fc00000u; constexpr u64 f32_non_sign_mask = 0x7fffffffu; @@ -341,9 +343,18 @@ void EmitX64::EmitFPAbs64(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, result); } +void EmitX64::EmitFPNeg16(EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); + + code.pxor(result, code.MConst(xword, f16_negative_zero)); + + ctx.reg_alloc.DefineValue(inst, result); +} + void EmitX64::EmitFPNeg32(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); + const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); code.pxor(result, code.MConst(xword, f32_negative_zero)); @@ -352,7 +363,7 @@ void EmitX64::EmitFPNeg32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitFPNeg64(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); + const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); code.pxor(result, code.MConst(xword, f64_negative_zero)); diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index 35c8d07b..75eb7b86 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -1880,11 +1880,17 @@ U32U64 IREmitter::FPMulX(const U32U64& a, const U32U64& b) { } } -U32U64 IREmitter::FPNeg(const U32U64& a) { - if (a.GetType() == Type::U32) { +U16U32U64 IREmitter::FPNeg(const U16U32U64& a) { + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPNeg16, a); + case Type::U32: return Inst(Opcode::FPNeg32, a); - } else { + case Type::U64: return Inst(Opcode::FPNeg64, a); + default: + UNREACHABLE(); + return U16U32U64{}; } } diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index 0e29d716..fa33d21a 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -303,7 +303,7 @@ public: U32U64 FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled); U32U64 FPMulAdd(const U32U64& addend, const U32U64& op1, const U32U64& op2, bool fpcr_controlled); U32U64 FPMulX(const U32U64& a, const U32U64& b); - U32U64 FPNeg(const U32U64& a); + U16U32U64 FPNeg(const U16U32U64& a); U32U64 FPRecipEstimate(const U32U64& a); U16U32U64 FPRecipExponent(const U16U32U64& a); U32U64 FPRecipStepFused(const U32U64& a, const U32U64& b); diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index ca87994a..81205e13 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -482,6 +482,7 @@ OPCODE(FPMulAdd32, U32, U32, OPCODE(FPMulAdd64, U64, U64, U64, U64 ) OPCODE(FPMulX32, U32, U32, U32 ) OPCODE(FPMulX64, U64, U64, U64 ) +OPCODE(FPNeg16, U16, U16 ) OPCODE(FPNeg32, U32, U32 ) OPCODE(FPNeg64, U64, U64 ) OPCODE(FPRecipEstimate32, U32, U32 ) From 10abc77fad8e90e8b81ff96b74ec745d8b668d86 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 23 Mar 2019 13:23:31 -0400 Subject: [PATCH 2/5] A64: Handle half-precision floating point in scalar FNEG With the half-precision variant of the FPNeg opcode added, we can utilize it here to emulate the half-precision variant of FNEG. --- .../impl/floating_point_data_processing_one_register.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp b/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp index 342fd4c4..c0aff00c 100644 --- a/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp +++ b/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp @@ -36,12 +36,12 @@ bool TranslatorVisitor::FABS_float(Imm<2> type, Vec Vn, Vec Vd) { bool TranslatorVisitor::FNEG_float(Imm<2> type, Vec Vn, Vec Vd) { const auto datasize = FPGetDataSize(type); - if (!datasize || *datasize == 16) { + if (!datasize) { return UnallocatedEncoding(); } - const IR::U32U64 operand = V_scalar(*datasize, Vn); - const IR::U32U64 result = ir.FPNeg(operand); + const IR::U16U32U64 operand = V_scalar(*datasize, Vn); + const IR::U16U32U64 result = ir.FPNeg(operand); V_scalar(*datasize, Vd, result); return true; } From 8309ec7a9f7ccde6f02daf80cebf429fe679092a Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 23 Mar 2019 13:38:05 -0400 Subject: [PATCH 3/5] frontend/ir_emitter: Add half-precision variant of FPAbs --- src/backend/x64/emit_x64_floating_point.cpp | 14 ++++++++++++-- src/frontend/ir/ir_emitter.cpp | 12 +++++++++--- src/frontend/ir/ir_emitter.h | 2 +- src/frontend/ir/opcodes.inc | 1 + 4 files changed, 23 insertions(+), 6 deletions(-) diff --git a/src/backend/x64/emit_x64_floating_point.cpp b/src/backend/x64/emit_x64_floating_point.cpp index b06a9eeb..544df20e 100644 --- a/src/backend/x64/emit_x64_floating_point.cpp +++ b/src/backend/x64/emit_x64_floating_point.cpp @@ -39,6 +39,7 @@ namespace { const Xbyak::Reg64 INVALID_REG = Xbyak::Reg64(-1); constexpr u64 f16_negative_zero = 0x8000; +constexpr u64 f16_non_sign_mask = 0x7fff; constexpr u64 f32_negative_zero = 0x80000000u; constexpr u64 f32_nan = 0x7fc00000u; @@ -325,9 +326,18 @@ void FPThreeOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) } // anonymous namespace +void EmitX64::EmitFPAbs16(EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); + + code.pand(result, code.MConst(xword, f16_non_sign_mask)); + + ctx.reg_alloc.DefineValue(inst, result); +} + void EmitX64::EmitFPAbs32(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); + const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); code.pand(result, code.MConst(xword, f32_non_sign_mask)); @@ -336,7 +346,7 @@ void EmitX64::EmitFPAbs32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitFPAbs64(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); + const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]); code.pand(result, code.MConst(xword, f64_non_sign_mask)); diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index 75eb7b86..43bc01b3 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -1773,11 +1773,17 @@ U128 IREmitter::ZeroVector() { return Inst(Opcode::ZeroVector); } -U32U64 IREmitter::FPAbs(const U32U64& a) { - if (a.GetType() == Type::U32) { +U16U32U64 IREmitter::FPAbs(const U16U32U64& a) { + switch (a.GetType()) { + case Type::U16: + return Inst(Opcode::FPAbs16, a); + case Type::U32: return Inst(Opcode::FPAbs32, a); - } else { + case Type::U64: return Inst(Opcode::FPAbs64, a); + default: + UNREACHABLE(); + return U16U32U64{}; } } diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index fa33d21a..4bbf8866 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -292,7 +292,7 @@ public: U128 VectorZeroUpper(const U128& a); U128 ZeroVector(); - U32U64 FPAbs(const U32U64& a); + U16U32U64 FPAbs(const U16U32U64& a); U32U64 FPAdd(const U32U64& a, const U32U64& b, bool fpcr_controlled); NZCV FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bool fpcr_controlled); U32U64 FPDiv(const U32U64& a, const U32U64& b, bool fpcr_controlled); diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index 81205e13..2a9b9291 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -460,6 +460,7 @@ OPCODE(VectorZeroUpper, U128, U128 OPCODE(ZeroVector, U128, ) // Floating-point operations +OPCODE(FPAbs16, U16, U16 ) OPCODE(FPAbs32, U32, U32 ) OPCODE(FPAbs64, U64, U64 ) OPCODE(FPAdd32, U32, U32, U32 ) From fe84ecb7808fbe37a20ac04593745f9e05214b30 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 23 Mar 2019 13:39:22 -0400 Subject: [PATCH 4/5] A64: Handle half-precision floating point in scalar FABS Now that we have the half-precision variant of the opcode added, we can simply handle the instruction instead of treating it as undefined. --- .../impl/floating_point_data_processing_one_register.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp b/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp index c0aff00c..e574c1f9 100644 --- a/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp +++ b/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp @@ -24,12 +24,12 @@ bool TranslatorVisitor::FMOV_float(Imm<2> type, Vec Vn, Vec Vd) { bool TranslatorVisitor::FABS_float(Imm<2> type, Vec Vn, Vec Vd) { const auto datasize = FPGetDataSize(type); - if (!datasize || *datasize == 16) { + if (!datasize) { return UnallocatedEncoding(); } - const IR::U32U64 operand = V_scalar(*datasize, Vn); - const IR::U32U64 result = ir.FPAbs(operand); + const IR::U16U32U64 operand = V_scalar(*datasize, Vn); + const IR::U16U32U64 result = ir.FPAbs(operand); V_scalar(*datasize, Vd, result); return true; } From 28a8b4d2102128318428c205075feda5bb4cea46 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 23 Mar 2019 13:45:19 -0400 Subject: [PATCH 5/5] A64: Handle half-precision floating point in scalar FMOV This is simply performing a scalar value transfer between registers without conversions, so this is trivial to handle as-is. --- .../impl/floating_point_data_processing_one_register.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp b/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp index e574c1f9..2a8c096e 100644 --- a/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp +++ b/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp @@ -12,13 +12,13 @@ namespace Dynarmic::A64 { bool TranslatorVisitor::FMOV_float(Imm<2> type, Vec Vn, Vec Vd) { const auto datasize = FPGetDataSize(type); - if (!datasize || *datasize == 16) { + if (!datasize) { return UnallocatedEncoding(); } - const IR::U128 operand = V(*datasize, Vn); + const IR::U16U32U64 operand = V_scalar(*datasize, Vn); - V(*datasize, Vd, operand); + V_scalar(*datasize, Vd, operand); return true; }