From b2f7a0e7ba0eb8ef96bf374655fe945a53b2acfc Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Apr 2019 08:06:18 -0400 Subject: [PATCH 1/8] A32: Implement ARM-mode SDIV/UDIV Now that we have Unicorn in place, we can freely implement instructions introduced in newer versions of the ARM architecture. --- src/CMakeLists.txt | 1 + src/frontend/A32/decoder/arm.inc | 4 ++ .../A32/disassembler/disassembler_arm.cpp | 8 ++++ .../A32/translate/translate_arm/divide.cpp | 42 +++++++++++++++++++ .../translate/translate_arm/translate_arm.h | 4 ++ tests/A32/fuzz_arm.cpp | 18 ++++++++ 6 files changed, 77 insertions(+) create mode 100644 src/frontend/A32/translate/translate_arm/divide.cpp diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index f460f742..3948ca17 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -98,6 +98,7 @@ add_library(dynarmic frontend/A32/translate/translate_arm/branch.cpp frontend/A32/translate/translate_arm/coprocessor.cpp frontend/A32/translate/translate_arm/data_processing.cpp + frontend/A32/translate/translate_arm/divide.cpp frontend/A32/translate/translate_arm/exception_generating.cpp frontend/A32/translate/translate_arm/extension.cpp frontend/A32/translate/translate_arm/load_store.cpp diff --git a/src/frontend/A32/decoder/arm.inc b/src/frontend/A32/decoder/arm.inc index dfd7a519..13f4b78a 100644 --- a/src/frontend/A32/decoder/arm.inc +++ b/src/frontend/A32/decoder/arm.inc @@ -187,6 +187,10 @@ INST(arm_SSAT16, "SSAT16", "cccc01101010vvvvdddd11110011nnnn INST(arm_USAT, "USAT", "cccc0110111vvvvvddddvvvvvr01nnnn") // v6 INST(arm_USAT16, "USAT16", "cccc01101110vvvvdddd11110011nnnn") // v6 +// Divide instructions +INST(arm_SDIV, "SDIV", "cccc01110001dddd1111mmmm0001nnnn") // v7a +INST(arm_UDIV, "UDIV", "cccc01110011dddd1111mmmm0001nnnn") // v7a + // Multiply (Normal) instructions INST(arm_MLA, "MLA", "cccc0000001Sddddaaaammmm1001nnnn") // v2 INST(arm_MUL, "MUL", "cccc0000000Sdddd0000mmmm1001nnnn") // v2 diff --git a/src/frontend/A32/disassembler/disassembler_arm.cpp b/src/frontend/A32/disassembler/disassembler_arm.cpp index bae46d19..d3717e8f 100644 --- a/src/frontend/A32/disassembler/disassembler_arm.cpp +++ b/src/frontend/A32/disassembler/disassembler_arm.cpp @@ -634,6 +634,14 @@ public: return fmt::format("usat16{} {}, #{}, {}", CondToString(cond), d, sat_imm, n); } + // Divide instructions + std::string arm_SDIV(Cond cond, Reg d, Reg m, Reg n) { + return fmt::format("sdiv{} {}, {}, {}", CondToString(cond), d, n, m); + } + std::string arm_UDIV(Cond cond, Reg d, Reg m, Reg n) { + return fmt::format("udiv{} {}, {}, {}", CondToString(cond), d, n, m); + } + // Multiply (Normal) instructions std::string arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n) { return fmt::format("mla{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), d, n, m, a); diff --git a/src/frontend/A32/translate/translate_arm/divide.cpp b/src/frontend/A32/translate/translate_arm/divide.cpp new file mode 100644 index 00000000..f60129cf --- /dev/null +++ b/src/frontend/A32/translate/translate_arm/divide.cpp @@ -0,0 +1,42 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2019 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#include "translate_arm.h" + +namespace Dynarmic::A32 { +namespace { +using DivideFunction = IR::U32U64 (IREmitter::*)(const IR::U32U64&, const IR::U32U64&); + +bool DivideOperation(ArmTranslatorVisitor& v, Cond cond, Reg d, Reg m, Reg n, + DivideFunction fn) { + if (d == Reg::PC || m == Reg::PC || n == Reg::PC) { + return v.UnpredictableInstruction(); + } + + if (!v.ConditionPassed(cond)) { + return true; + } + + const IR::U32 operand1 = v.ir.GetRegister(n); + const IR::U32 operand2 = v.ir.GetRegister(m); + const IR::U32 result = (v.ir.*fn)(operand1, operand2); + + v.ir.SetRegister(d, result); + return true; +} +} // Anonymous namespace + +// SDIV , , +bool ArmTranslatorVisitor::arm_SDIV(Cond cond, Reg d, Reg m, Reg n) { + return DivideOperation(*this, cond, d, m, n, &IREmitter::SignedDiv); +} + +// UDIV , , +bool ArmTranslatorVisitor::arm_UDIV(Cond cond, Reg d, Reg m, Reg n) { + return DivideOperation(*this, cond, d, m, n, &IREmitter::UnsignedDiv); +} + +} // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/translate_arm/translate_arm.h b/src/frontend/A32/translate/translate_arm/translate_arm.h index 0f7613a2..fff624b3 100644 --- a/src/frontend/A32/translate/translate_arm/translate_arm.h +++ b/src/frontend/A32/translate/translate_arm/translate_arm.h @@ -230,6 +230,10 @@ struct ArmTranslatorVisitor final { bool arm_USAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n); bool arm_USAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n); + // Divide instructions + bool arm_SDIV(Cond cond, Reg d, Reg m, Reg n); + bool arm_UDIV(Cond cond, Reg d, Reg m, Reg n); + // Multiply (Normal) instructions bool arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n); bool arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n); diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index 565be799..4358d966 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -812,6 +812,24 @@ TEST_CASE("Fuzz ARM extension instructions", "[JitX64][A32]") { } } +TEST_CASE("Fuzz ARM divide instructions", "[JitX64][A32]") { + const auto is_valid = [](u32 instr) { + return Bits<0, 3>(instr) != 0b1111 && + Bits<8, 11>(instr) != 0b1111 && + Bits<16, 19>(instr) != 0b1111; + }; + + const std::array instructions = { + InstructionGenerator("cccc01110001dddd1111mmmm0001nnnn", is_valid), // SDIV + InstructionGenerator("cccc01110011dddd1111mmmm0001nnnn", is_valid), // UDIV + }; + + FuzzJitArm(1, 1, 5000, [&instructions]() -> u32 { + return instructions[RandInt(0, instructions.size() - 1)].Generate(); + }); +} + + TEST_CASE("Fuzz ARM multiply instructions", "[JitX64][A32]") { const auto validate_d_m_n = [](u32 inst) -> bool { return Bits<16, 19>(inst) != 15 && From 7305d1322156ede482d3c269d33766dd43c6691a Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Apr 2019 10:16:18 -0400 Subject: [PATCH 2/8] A32: Implement ARM-mode RBIT --- src/frontend/A32/decoder/arm.inc | 1 + .../A32/disassembler/disassembler_arm.cpp | 3 ++ .../A32/translate/translate_arm/reversal.cpp | 30 +++++++++++++++++++ .../translate/translate_arm/translate_arm.h | 1 + tests/A32/fuzz_arm.cpp | 7 +++-- 5 files changed, 39 insertions(+), 3 deletions(-) diff --git a/src/frontend/A32/decoder/arm.inc b/src/frontend/A32/decoder/arm.inc index 13f4b78a..5666b2c7 100644 --- a/src/frontend/A32/decoder/arm.inc +++ b/src/frontend/A32/decoder/arm.inc @@ -177,6 +177,7 @@ INST(arm_PKHBT, "PKHBT", "cccc01101000nnnnddddvvvvv001mmmm INST(arm_PKHTB, "PKHTB", "cccc01101000nnnnddddvvvvv101mmmm") // v6K // Reversal instructions +INST(arm_RBIT, "RBIT", "cccc011011111111dddd11110011mmmm") // v6T2 INST(arm_REV, "REV", "cccc011010111111dddd11110011mmmm") // v6 INST(arm_REV16, "REV16", "cccc011010111111dddd11111011mmmm") // v6 INST(arm_REVSH, "REVSH", "cccc011011111111dddd11111011mmmm") // v6 diff --git a/src/frontend/A32/disassembler/disassembler_arm.cpp b/src/frontend/A32/disassembler/disassembler_arm.cpp index d3717e8f..b3e7ef90 100644 --- a/src/frontend/A32/disassembler/disassembler_arm.cpp +++ b/src/frontend/A32/disassembler/disassembler_arm.cpp @@ -589,6 +589,9 @@ public: std::string arm_NOP() { return "nop"; } + std::string arm_RBIT(Cond cond, Reg d, Reg m) { + return fmt::format("rbit{} {}, {}", CondToString(cond), d, m); + } std::string arm_SEL(Cond cond, Reg n, Reg d, Reg m) { return fmt::format("sel{} {}, {}, {}", CondToString(cond), d, n, m); } diff --git a/src/frontend/A32/translate/translate_arm/reversal.cpp b/src/frontend/A32/translate/translate_arm/reversal.cpp index ae7f4506..d75ade41 100644 --- a/src/frontend/A32/translate/translate_arm/reversal.cpp +++ b/src/frontend/A32/translate/translate_arm/reversal.cpp @@ -8,6 +8,36 @@ namespace Dynarmic::A32 { +// RBIT , +bool ArmTranslatorVisitor::arm_RBIT(Cond cond, Reg d, Reg m) { + if (d == Reg::PC || m == Reg::PC) { + return UnpredictableInstruction(); + } + + if (!ConditionPassed(cond)) { + return true; + } + + const IR::U32 swapped = ir.ByteReverseWord(ir.GetRegister(m)); + + // ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4) + const IR::U32 first_lsr = ir.LogicalShiftRight(ir.And(swapped, ir.Imm32(0xF0F0F0F0)), ir.Imm8(4)); + const IR::U32 first_lsl = ir.LogicalShiftLeft(ir.And(swapped, ir.Imm32(0x0F0F0F0F)), ir.Imm8(4)); + const IR::U32 corrected = ir.Or(first_lsl, first_lsr); + + // ((x & 0x88888888) >> 3) | ((x & 0x44444444) >> 1) | + // ((x & 0x22222222) << 1) | ((x & 0x11111111) << 3) + const IR::U32 second_lsr = ir.LogicalShiftRight(ir.And(corrected, ir.Imm32(0x88888888)), ir.Imm8(3)); + const IR::U32 third_lsr = ir.LogicalShiftRight(ir.And(corrected, ir.Imm32(0x44444444)), ir.Imm8(1)); + const IR::U32 second_lsl = ir.LogicalShiftLeft(ir.And(corrected, ir.Imm32(0x22222222)), ir.Imm8(1)); + const IR::U32 third_lsl = ir.LogicalShiftLeft(ir.And(corrected, ir.Imm32(0x11111111)), ir.Imm8(3)); + + const IR::U32 result = ir.Or(ir.Or(ir.Or(second_lsr, third_lsr), second_lsl), third_lsl); + + ir.SetRegister(d, result); + return true; +} + // REV , bool ArmTranslatorVisitor::arm_REV(Cond cond, Reg d, Reg m) { if (d == Reg::PC || m == Reg::PC) { diff --git a/src/frontend/A32/translate/translate_arm/translate_arm.h b/src/frontend/A32/translate/translate_arm/translate_arm.h index fff624b3..d92a0050 100644 --- a/src/frontend/A32/translate/translate_arm/translate_arm.h +++ b/src/frontend/A32/translate/translate_arm/translate_arm.h @@ -209,6 +209,7 @@ struct ArmTranslatorVisitor final { // Miscellaneous instructions bool arm_CLZ(Cond cond, Reg d, Reg m); bool arm_NOP() { return true; } + bool arm_RBIT(Cond cond, Reg d, Reg m); bool arm_SEL(Cond cond, Reg n, Reg d, Reg m); // Unsigned sum of absolute difference functions diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index 4358d966..6515c821 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -763,9 +763,10 @@ TEST_CASE("Fuzz ARM reversal instructions", "[JitX64][A32]") { }; const std::array rev_instructions = { - InstructionGenerator("cccc011010111111dddd11110011mmmm", is_valid), - InstructionGenerator("cccc011010111111dddd11111011mmmm", is_valid), - InstructionGenerator("cccc011011111111dddd11111011mmmm", is_valid), + InstructionGenerator("cccc011011111111dddd11110011mmmm", is_valid), // RBIT + InstructionGenerator("cccc011010111111dddd11110011mmmm", is_valid), // REV + InstructionGenerator("cccc011010111111dddd11111011mmmm", is_valid), // REV16 + InstructionGenerator("cccc011011111111dddd11111011mmmm", is_valid), // REVSH }; SECTION("Reverse tests") { From fab3a59e05ccf2fa084ae85b342636154fa30b0c Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Apr 2019 11:11:44 -0400 Subject: [PATCH 3/8] A32: Implement ARM-mode BFC --- src/frontend/A32/decoder/arm.inc | 1 + .../A32/disassembler/disassembler_arm.cpp | 3 +++ .../A32/translate/translate_arm/misc.cpp | 22 +++++++++++++++++ .../translate/translate_arm/translate_arm.h | 1 + tests/A32/fuzz_arm.cpp | 24 +++++++++++++------ 5 files changed, 44 insertions(+), 7 deletions(-) diff --git a/src/frontend/A32/decoder/arm.inc b/src/frontend/A32/decoder/arm.inc index 5666b2c7..58214876 100644 --- a/src/frontend/A32/decoder/arm.inc +++ b/src/frontend/A32/decoder/arm.inc @@ -164,6 +164,7 @@ INST(arm_STMIB, "STMIB", "cccc100110w0nnnnxxxxxxxxxxxxxxxx INST(arm_STM_usr, "STM (usr reg)", "----100--100--------------------") // all // Miscellaneous instructions +INST(arm_BFC, "BFC", "cccc0111110vvvvvddddvvvvv0011111") // v6T2 INST(arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm") // v5 INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6 diff --git a/src/frontend/A32/disassembler/disassembler_arm.cpp b/src/frontend/A32/disassembler/disassembler_arm.cpp index b3e7ef90..57317539 100644 --- a/src/frontend/A32/disassembler/disassembler_arm.cpp +++ b/src/frontend/A32/disassembler/disassembler_arm.cpp @@ -583,6 +583,9 @@ public: std::string arm_STM_usr() { return "ice"; } // Miscellaneous instructions + std::string arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) { + return fmt::format("bfc{} {}, #{}, #{}", CondToString(cond), d, lsb, msb - lsb + 1); + } std::string arm_CLZ(Cond cond, Reg d, Reg m) { return fmt::format("clz{} {}, {}", CondToString(cond), d, m); } diff --git a/src/frontend/A32/translate/translate_arm/misc.cpp b/src/frontend/A32/translate/translate_arm/misc.cpp index 100c1271..a5b38acc 100644 --- a/src/frontend/A32/translate/translate_arm/misc.cpp +++ b/src/frontend/A32/translate/translate_arm/misc.cpp @@ -4,10 +4,32 @@ * General Public License version 2 or any later version. */ +#include "common/bit_util.h" #include "translate_arm.h" namespace Dynarmic::A32 { +// BFC , #, # +bool ArmTranslatorVisitor::arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) { + if (d == Reg::PC) { + return UnpredictableInstruction(); + } + if (msb < lsb) { + return UnpredictableInstruction(); + } + + if (!ConditionPassed(cond)) { + return true; + } + + const u32 mask = ~(Common::Ones(msb - lsb + 1) << lsb); + const IR::U32 operand = ir.GetRegister(d); + const IR::U32 result = ir.And(operand, ir.Imm32(mask)); + + ir.SetRegister(d, result); + return true; +} + // CLZ , bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) { if (d == Reg::PC || m == Reg::PC) { diff --git a/src/frontend/A32/translate/translate_arm/translate_arm.h b/src/frontend/A32/translate/translate_arm/translate_arm.h index d92a0050..77bfa932 100644 --- a/src/frontend/A32/translate/translate_arm/translate_arm.h +++ b/src/frontend/A32/translate/translate_arm/translate_arm.h @@ -207,6 +207,7 @@ struct ArmTranslatorVisitor final { bool arm_STM_usr(); // Miscellaneous instructions + bool arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb); bool arm_CLZ(Cond cond, Reg d, Reg m); bool arm_NOP() { return true; } bool arm_RBIT(Cond cond, Reg d, Reg m); diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index 6515c821..284c4876 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -1080,18 +1080,28 @@ TEST_CASE("VFP: VPUSH, VPOP", "[JitX64][.vfp][A32]") { } TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") { - const auto is_clz_valid = [](u32 instr) -> bool { + const auto is_bfc_valid = [](u32 instr) { + if (Bits<12, 15>(instr) == 0b1111) { + // Destination register may not be the PC. + return false; + } + // msb must be greater than or equal to the lsb, + // otherwise the instruction is UNPREDICTABLE. + return Bits<16, 20>(instr) >= Bits<7, 11>(instr); + }; + const auto is_clz_valid = [](u32 instr) { // R15 as Rd, or Rm is UNPREDICTABLE return Bits<0, 3>(instr) != 0b1111 && Bits<12, 15>(instr) != 0b1111; }; - const InstructionGenerator clz_instr = InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid); // CLZ + const std::array instructions = { + InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_valid), // BFC + InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid), // CLZ + }; - SECTION("Fuzz CLZ") { - FuzzJitArm(1, 1, 1000, [&clz_instr]() -> u32 { - return clz_instr.Generate(); - }); - } + FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 { + return instructions[RandInt(0, instructions.size() - 1)].Generate(); + }); } TEST_CASE("Test ARM MSR instructions", "[JitX64][A32]") { From 2970b34e3cf838958f935e86bb006c531b50844d Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Apr 2019 11:57:58 -0400 Subject: [PATCH 4/8] A32: Implement ARM-mode BFI --- src/frontend/A32/decoder/arm.inc | 1 + .../A32/disassembler/disassembler_arm.cpp | 3 +++ .../A32/translate/translate_arm/misc.cpp | 23 +++++++++++++++++++ .../translate/translate_arm/translate_arm.h | 1 + tests/A32/fuzz_arm.cpp | 7 +++--- 5 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/frontend/A32/decoder/arm.inc b/src/frontend/A32/decoder/arm.inc index 58214876..9772776b 100644 --- a/src/frontend/A32/decoder/arm.inc +++ b/src/frontend/A32/decoder/arm.inc @@ -165,6 +165,7 @@ INST(arm_STM_usr, "STM (usr reg)", "----100--100-------------------- // Miscellaneous instructions INST(arm_BFC, "BFC", "cccc0111110vvvvvddddvvvvv0011111") // v6T2 +INST(arm_BFI, "BFI", "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2 INST(arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm") // v5 INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6 diff --git a/src/frontend/A32/disassembler/disassembler_arm.cpp b/src/frontend/A32/disassembler/disassembler_arm.cpp index 57317539..c969ce3e 100644 --- a/src/frontend/A32/disassembler/disassembler_arm.cpp +++ b/src/frontend/A32/disassembler/disassembler_arm.cpp @@ -586,6 +586,9 @@ public: std::string arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) { return fmt::format("bfc{} {}, #{}, #{}", CondToString(cond), d, lsb, msb - lsb + 1); } + std::string arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n) { + return fmt::format("bfi{} {}, {}, #{}, #{}", CondToString(cond), d, n, lsb, msb - lsb + 1); + } std::string arm_CLZ(Cond cond, Reg d, Reg m) { return fmt::format("clz{} {}, {}", CondToString(cond), d, m); } diff --git a/src/frontend/A32/translate/translate_arm/misc.cpp b/src/frontend/A32/translate/translate_arm/misc.cpp index a5b38acc..b7ecf4bd 100644 --- a/src/frontend/A32/translate/translate_arm/misc.cpp +++ b/src/frontend/A32/translate/translate_arm/misc.cpp @@ -30,6 +30,29 @@ bool ArmTranslatorVisitor::arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) { return true; } +// BFI , , #, # +bool ArmTranslatorVisitor::arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n) { + if (d == Reg::PC) { + return UnpredictableInstruction(); + } + if (msb < lsb) { + return UnpredictableInstruction(); + } + + if (!ConditionPassed(cond)) { + return true; + } + + const u32 inclusion_mask = Common::Ones(msb - lsb + 1) << lsb; + const u32 exclusion_mask = ~inclusion_mask; + const IR::U32 operand1 = ir.And(ir.GetRegister(d), ir.Imm32(exclusion_mask)); + const IR::U32 operand2 = ir.And(ir.LogicalShiftLeft(ir.GetRegister(n), ir.Imm8(lsb)), ir.Imm32(inclusion_mask)); + const IR::U32 result = ir.Or(operand1, operand2); + + ir.SetRegister(d, result); + return true; +} + // CLZ , bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) { if (d == Reg::PC || m == Reg::PC) { diff --git a/src/frontend/A32/translate/translate_arm/translate_arm.h b/src/frontend/A32/translate/translate_arm/translate_arm.h index 77bfa932..7aa2e5e8 100644 --- a/src/frontend/A32/translate/translate_arm/translate_arm.h +++ b/src/frontend/A32/translate/translate_arm/translate_arm.h @@ -208,6 +208,7 @@ struct ArmTranslatorVisitor final { // Miscellaneous instructions bool arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb); + bool arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n); bool arm_CLZ(Cond cond, Reg d, Reg m); bool arm_NOP() { return true; } bool arm_RBIT(Cond cond, Reg d, Reg m); diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index 284c4876..d1e77585 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -1080,7 +1080,7 @@ TEST_CASE("VFP: VPUSH, VPOP", "[JitX64][.vfp][A32]") { } TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") { - const auto is_bfc_valid = [](u32 instr) { + const auto is_bfc_bfi_valid = [](u32 instr) { if (Bits<12, 15>(instr) == 0b1111) { // Destination register may not be the PC. return false; @@ -1095,8 +1095,9 @@ TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") { }; const std::array instructions = { - InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_valid), // BFC - InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid), // CLZ + InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_bfi_valid), // BFC + InstructionGenerator("cccc0111110vvvvvddddvvvvv001nnnn", is_bfc_bfi_valid), // BFI + InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid), // CLZ }; FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 { From 47218ee65d652137119a47181941d3a34898afe4 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Apr 2019 12:47:34 -0400 Subject: [PATCH 5/8] A32: Implement ARM-mode UBFX --- src/frontend/A32/decoder/arm.inc | 1 + .../A32/disassembler/disassembler_arm.cpp | 3 +++ .../A32/translate/translate_arm/misc.cpp | 23 +++++++++++++++++++ .../translate/translate_arm/translate_arm.h | 1 + tests/A32/fuzz_arm.cpp | 11 +++++++++ 5 files changed, 39 insertions(+) diff --git a/src/frontend/A32/decoder/arm.inc b/src/frontend/A32/decoder/arm.inc index 9772776b..ee9f7de1 100644 --- a/src/frontend/A32/decoder/arm.inc +++ b/src/frontend/A32/decoder/arm.inc @@ -169,6 +169,7 @@ INST(arm_BFI, "BFI", "cccc0111110vvvvvddddvvvvv001nnnn INST(arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm") // v5 INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6 +INST(arm_UBFX, "UBFX", "cccc0111111wwwwwddddvvvvv101nnnn") // v6T2 // Unsigned Sum of Absolute Differences instructions INST(arm_USAD8, "USAD8", "cccc01111000dddd1111mmmm0001nnnn") // v6 diff --git a/src/frontend/A32/disassembler/disassembler_arm.cpp b/src/frontend/A32/disassembler/disassembler_arm.cpp index c969ce3e..a6c906fc 100644 --- a/src/frontend/A32/disassembler/disassembler_arm.cpp +++ b/src/frontend/A32/disassembler/disassembler_arm.cpp @@ -601,6 +601,9 @@ public: std::string arm_SEL(Cond cond, Reg n, Reg d, Reg m) { return fmt::format("sel{} {}, {}, {}", CondToString(cond), d, n, m); } + std::string arm_UBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) { + return fmt::format("ubfx{} {}, {}, #{}, #{}", CondToString(cond), d, n, lsb, widthm1 + 1); + } // Unsigned sum of absolute difference functions std::string arm_USAD8(Cond cond, Reg d, Reg m, Reg n) { diff --git a/src/frontend/A32/translate/translate_arm/misc.cpp b/src/frontend/A32/translate/translate_arm/misc.cpp index b7ecf4bd..9670875d 100644 --- a/src/frontend/A32/translate/translate_arm/misc.cpp +++ b/src/frontend/A32/translate/translate_arm/misc.cpp @@ -85,4 +85,27 @@ bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) { return true; } +// UBFX , , #, # +bool ArmTranslatorVisitor::arm_UBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) { + if (d == Reg::PC || n == Reg::PC) { + return UnpredictableInstruction(); + } + + const u32 msb = u32{lsb} + widthm1; + if (msb >= Common::BitSize()) { + return UnpredictableInstruction(); + } + + if (!ConditionPassed(cond)) { + return true; + } + + const IR::U32 operand = ir.GetRegister(n); + const IR::U32 mask = ir.Imm32(Common::Ones(widthm1 + 1)); + const IR::U32 result = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(lsb)), mask); + + ir.SetRegister(d, result); + return true; +} + } // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/translate_arm/translate_arm.h b/src/frontend/A32/translate/translate_arm/translate_arm.h index 7aa2e5e8..b1cfac68 100644 --- a/src/frontend/A32/translate/translate_arm/translate_arm.h +++ b/src/frontend/A32/translate/translate_arm/translate_arm.h @@ -213,6 +213,7 @@ struct ArmTranslatorVisitor final { bool arm_NOP() { return true; } bool arm_RBIT(Cond cond, Reg d, Reg m); bool arm_SEL(Cond cond, Reg n, Reg d, Reg m); + bool arm_UBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n); // Unsigned sum of absolute difference functions bool arm_USAD8(Cond cond, Reg d, Reg m, Reg n); diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index d1e77585..87029a9f 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -1093,11 +1093,22 @@ TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") { // R15 as Rd, or Rm is UNPREDICTABLE return Bits<0, 3>(instr) != 0b1111 && Bits<12, 15>(instr) != 0b1111; }; + const auto is_ubfx_valid = [](u32 instr) { + const u32 lsb = Bits<7, 11>(instr); + const u32 widthm1 = Bits<16, 20>(instr); + const u32 msb = lsb + widthm1; + + // Rd or Rn as R15 or the case where msb > 32 is UNPREDICTABLE. + return Bits<0, 3>(instr) != 0b1111 && + Bits<12, 15>(instr) != 0b1111 && + msb < Dynarmic::Common::BitSize(); + }; const std::array instructions = { InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_bfi_valid), // BFC InstructionGenerator("cccc0111110vvvvvddddvvvvv001nnnn", is_bfc_bfi_valid), // BFI InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid), // CLZ + InstructionGenerator("cccc0111111wwwwwddddvvvvv101nnnn", is_ubfx_valid), // UBFX }; FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 { From 877fa0f8c39101c0b543ed43c350d7d66c04200c Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Apr 2019 13:14:35 -0400 Subject: [PATCH 6/8] A32: Implement ARM-mode SBFX --- src/frontend/A32/decoder/arm.inc | 1 + .../A32/disassembler/disassembler_arm.cpp | 3 +++ .../A32/translate/translate_arm/misc.cpp | 27 +++++++++++++++++++ .../translate/translate_arm/translate_arm.h | 1 + tests/A32/fuzz_arm.cpp | 5 ++-- 5 files changed, 35 insertions(+), 2 deletions(-) diff --git a/src/frontend/A32/decoder/arm.inc b/src/frontend/A32/decoder/arm.inc index ee9f7de1..d8ba8d32 100644 --- a/src/frontend/A32/decoder/arm.inc +++ b/src/frontend/A32/decoder/arm.inc @@ -168,6 +168,7 @@ INST(arm_BFC, "BFC", "cccc0111110vvvvvddddvvvvv0011111 INST(arm_BFI, "BFI", "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2 INST(arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm") // v5 INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K +INST(arm_SBFX, "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn") // v6T2 INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6 INST(arm_UBFX, "UBFX", "cccc0111111wwwwwddddvvvvv101nnnn") // v6T2 diff --git a/src/frontend/A32/disassembler/disassembler_arm.cpp b/src/frontend/A32/disassembler/disassembler_arm.cpp index a6c906fc..be0bbe21 100644 --- a/src/frontend/A32/disassembler/disassembler_arm.cpp +++ b/src/frontend/A32/disassembler/disassembler_arm.cpp @@ -598,6 +598,9 @@ public: std::string arm_RBIT(Cond cond, Reg d, Reg m) { return fmt::format("rbit{} {}, {}", CondToString(cond), d, m); } + std::string arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) { + return fmt::format("sbfx{} {}, {}, #{}, #{}", CondToString(cond), d, n, lsb, widthm1 + 1); + } std::string arm_SEL(Cond cond, Reg n, Reg d, Reg m) { return fmt::format("sel{} {}, {}, {}", CondToString(cond), d, n, m); } diff --git a/src/frontend/A32/translate/translate_arm/misc.cpp b/src/frontend/A32/translate/translate_arm/misc.cpp index 9670875d..88026633 100644 --- a/src/frontend/A32/translate/translate_arm/misc.cpp +++ b/src/frontend/A32/translate/translate_arm/misc.cpp @@ -67,6 +67,33 @@ bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) { return true; } +// SBFX , , #, # +bool ArmTranslatorVisitor::arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) { + if (d == Reg::PC || n == Reg::PC) { + return UnpredictableInstruction(); + } + + const u32 msb = u32{lsb} + widthm1; + if (msb >= Common::BitSize()) { + return UnpredictableInstruction(); + } + + if (!ConditionPassed(cond)) { + return true; + } + + constexpr size_t max_width = Common::BitSize(); + const u8 width = widthm1 + 1; + const u8 left_shift_amount = static_cast(max_width - width - lsb); + const u8 right_shift_amount = static_cast(max_width - width); + const IR::U32 operand = ir.GetRegister(n); + const IR::U32 tmp = ir.LogicalShiftLeft(operand, ir.Imm8(left_shift_amount)); + const IR::U32 result = ir.ArithmeticShiftRight(tmp, ir.Imm8(right_shift_amount)); + + ir.SetRegister(d, result); + return true; +} + // SEL , , bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) { if (n == Reg::PC || d == Reg::PC || m == Reg::PC) { diff --git a/src/frontend/A32/translate/translate_arm/translate_arm.h b/src/frontend/A32/translate/translate_arm/translate_arm.h index b1cfac68..ff8db053 100644 --- a/src/frontend/A32/translate/translate_arm/translate_arm.h +++ b/src/frontend/A32/translate/translate_arm/translate_arm.h @@ -212,6 +212,7 @@ struct ArmTranslatorVisitor final { bool arm_CLZ(Cond cond, Reg d, Reg m); bool arm_NOP() { return true; } bool arm_RBIT(Cond cond, Reg d, Reg m); + bool arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n); bool arm_SEL(Cond cond, Reg n, Reg d, Reg m); bool arm_UBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n); diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index 87029a9f..58d0df20 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -1093,7 +1093,7 @@ TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") { // R15 as Rd, or Rm is UNPREDICTABLE return Bits<0, 3>(instr) != 0b1111 && Bits<12, 15>(instr) != 0b1111; }; - const auto is_ubfx_valid = [](u32 instr) { + const auto is_extract_valid = [](u32 instr) { const u32 lsb = Bits<7, 11>(instr); const u32 widthm1 = Bits<16, 20>(instr); const u32 msb = lsb + widthm1; @@ -1108,7 +1108,8 @@ TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") { InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_bfi_valid), // BFC InstructionGenerator("cccc0111110vvvvvddddvvvvv001nnnn", is_bfc_bfi_valid), // BFI InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid), // CLZ - InstructionGenerator("cccc0111111wwwwwddddvvvvv101nnnn", is_ubfx_valid), // UBFX + InstructionGenerator("cccc0111101wwwwwddddvvvvv101nnnn", is_extract_valid), // SBFX + InstructionGenerator("cccc0111111wwwwwddddvvvvv101nnnn", is_extract_valid), // UBFX }; FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 { From 8b338b7defc389561f67b79b0b4a9fa745e3b98a Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Apr 2019 14:14:31 -0400 Subject: [PATCH 7/8] A32: Implement ARM-mode MOVT --- src/frontend/A32/decoder/arm.inc | 1 + .../A32/disassembler/disassembler_arm.cpp | 3 +++ .../A32/translate/translate_arm/misc.cpp | 18 ++++++++++++++++++ .../translate/translate_arm/translate_arm.h | 1 + tests/A32/fuzz_arm.cpp | 4 ++++ 5 files changed, 27 insertions(+) diff --git a/src/frontend/A32/decoder/arm.inc b/src/frontend/A32/decoder/arm.inc index d8ba8d32..54b761bb 100644 --- a/src/frontend/A32/decoder/arm.inc +++ b/src/frontend/A32/decoder/arm.inc @@ -167,6 +167,7 @@ INST(arm_STM_usr, "STM (usr reg)", "----100--100-------------------- INST(arm_BFC, "BFC", "cccc0111110vvvvvddddvvvvv0011111") // v6T2 INST(arm_BFI, "BFI", "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2 INST(arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm") // v5 +INST(arm_MOVT, "MOVT", "cccc00110100vvvvddddvvvvvvvvvvvv") // v6T2 INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K INST(arm_SBFX, "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn") // v6T2 INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6 diff --git a/src/frontend/A32/disassembler/disassembler_arm.cpp b/src/frontend/A32/disassembler/disassembler_arm.cpp index be0bbe21..145c6381 100644 --- a/src/frontend/A32/disassembler/disassembler_arm.cpp +++ b/src/frontend/A32/disassembler/disassembler_arm.cpp @@ -592,6 +592,9 @@ public: std::string arm_CLZ(Cond cond, Reg d, Reg m) { return fmt::format("clz{} {}, {}", CondToString(cond), d, m); } + std::string arm_MOVT(Cond cond, Imm4 imm4, Reg d, Imm12 imm12) { + return fmt::format("movt{} {}, #{}", CondToString(cond), d, (imm4 << 12) | imm12); + } std::string arm_NOP() { return "nop"; } diff --git a/src/frontend/A32/translate/translate_arm/misc.cpp b/src/frontend/A32/translate/translate_arm/misc.cpp index 88026633..0dceeae9 100644 --- a/src/frontend/A32/translate/translate_arm/misc.cpp +++ b/src/frontend/A32/translate/translate_arm/misc.cpp @@ -67,6 +67,24 @@ bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) { return true; } +// MOVT , # +bool ArmTranslatorVisitor::arm_MOVT(Cond cond, Imm4 imm4, Reg d, Imm12 imm12) { + if (d == Reg::PC) { + return UnpredictableInstruction(); + } + + if (!ConditionPassed(cond)) { + return true; + } + + const IR::U32 imm16 = ir.Imm32(((u32(imm4) << 12 | u32(imm12)) << 16)); + const IR::U32 operand = ir.GetRegister(d); + const IR::U32 result = ir.Or(ir.And(operand, ir.Imm32(0x0000FFFFU)), imm16); + + ir.SetRegister(d, result); + return true; +} + // SBFX , , #, # bool ArmTranslatorVisitor::arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) { if (d == Reg::PC || n == Reg::PC) { diff --git a/src/frontend/A32/translate/translate_arm/translate_arm.h b/src/frontend/A32/translate/translate_arm/translate_arm.h index ff8db053..6165109b 100644 --- a/src/frontend/A32/translate/translate_arm/translate_arm.h +++ b/src/frontend/A32/translate/translate_arm/translate_arm.h @@ -210,6 +210,7 @@ struct ArmTranslatorVisitor final { bool arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb); bool arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n); bool arm_CLZ(Cond cond, Reg d, Reg m); + bool arm_MOVT(Cond cond, Imm4 imm4, Reg d, Imm12 imm12); bool arm_NOP() { return true; } bool arm_RBIT(Cond cond, Reg d, Reg m); bool arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n); diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index 58d0df20..c2044765 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -1103,11 +1103,15 @@ TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") { Bits<12, 15>(instr) != 0b1111 && msb < Dynarmic::Common::BitSize(); }; + const auto is_movt_valid = [](u32 instr) { + return Bits<12, 15>(instr) != 0b1111; + }; const std::array instructions = { InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_bfi_valid), // BFC InstructionGenerator("cccc0111110vvvvvddddvvvvv001nnnn", is_bfc_bfi_valid), // BFI InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid), // CLZ + InstructionGenerator("cccc00110100vvvvddddvvvvvvvvvvvv", is_movt_valid), // MOVT InstructionGenerator("cccc0111101wwwwwddddvvvvv101nnnn", is_extract_valid), // SBFX InstructionGenerator("cccc0111111wwwwwddddvvvvv101nnnn", is_extract_valid), // UBFX }; From 7fc3bd689df92d75ce7b89d16a6b1a7f1b43add5 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sun, 21 Apr 2019 21:37:27 -0400 Subject: [PATCH 8/8] A32: Implement ARM-mode MLS --- src/frontend/A32/decoder/arm.inc | 1 + .../A32/disassembler/disassembler_arm.cpp | 3 +++ .../A32/translate/translate_arm/multiply.cpp | 19 +++++++++++++++++++ .../translate/translate_arm/translate_arm.h | 1 + tests/A32/fuzz_arm.cpp | 1 + 5 files changed, 25 insertions(+) diff --git a/src/frontend/A32/decoder/arm.inc b/src/frontend/A32/decoder/arm.inc index 54b761bb..8aa57043 100644 --- a/src/frontend/A32/decoder/arm.inc +++ b/src/frontend/A32/decoder/arm.inc @@ -199,6 +199,7 @@ INST(arm_UDIV, "UDIV", "cccc01110011dddd1111mmmm0001nnnn // Multiply (Normal) instructions INST(arm_MLA, "MLA", "cccc0000001Sddddaaaammmm1001nnnn") // v2 +INST(arm_MLS, "MLS", "cccc00000110ddddaaaammmm1001nnnn") // v6T2 INST(arm_MUL, "MUL", "cccc0000000Sdddd0000mmmm1001nnnn") // v2 // Multiply (Long) instructions diff --git a/src/frontend/A32/disassembler/disassembler_arm.cpp b/src/frontend/A32/disassembler/disassembler_arm.cpp index 145c6381..598c9ae0 100644 --- a/src/frontend/A32/disassembler/disassembler_arm.cpp +++ b/src/frontend/A32/disassembler/disassembler_arm.cpp @@ -664,6 +664,9 @@ public: std::string arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n) { return fmt::format("mla{}{} {}, {}, {}, {}", S ? "s" : "", CondToString(cond), d, n, m, a); } + std::string arm_MLS(Cond cond, Reg d, Reg a, Reg m, Reg n) { + return fmt::format("mls{} {}, {}, {}, {}", CondToString(cond), d, n, m, a); + } std::string arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n) { return fmt::format("mul{}{} {}, {}, {}", S ? "s" : "", CondToString(cond), d, n, m); } diff --git a/src/frontend/A32/translate/translate_arm/multiply.cpp b/src/frontend/A32/translate/translate_arm/multiply.cpp index e6ac9215..334fe2a6 100644 --- a/src/frontend/A32/translate/translate_arm/multiply.cpp +++ b/src/frontend/A32/translate/translate_arm/multiply.cpp @@ -28,6 +28,25 @@ bool ArmTranslatorVisitor::arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n return true; } +// MLS , , , +bool ArmTranslatorVisitor::arm_MLS(Cond cond, Reg d, Reg a, Reg m, Reg n) { + if (d == Reg::PC || a == Reg::PC || m == Reg::PC || n == Reg::PC) { + return UnpredictableInstruction(); + } + + if (!ConditionPassed(cond)) { + return true; + } + + const IR::U32 operand1 = ir.GetRegister(n); + const IR::U32 operand2 = ir.GetRegister(m); + const IR::U32 operand3 = ir.GetRegister(a); + const IR::U32 result = ir.Sub(operand3, ir.Mul(operand1, operand2)); + + ir.SetRegister(d, result); + return true; +} + // MUL{S} , , bool ArmTranslatorVisitor::arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n) { if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { diff --git a/src/frontend/A32/translate/translate_arm/translate_arm.h b/src/frontend/A32/translate/translate_arm/translate_arm.h index 6165109b..dd8f3cb2 100644 --- a/src/frontend/A32/translate/translate_arm/translate_arm.h +++ b/src/frontend/A32/translate/translate_arm/translate_arm.h @@ -242,6 +242,7 @@ struct ArmTranslatorVisitor final { // Multiply (Normal) instructions bool arm_MLA(Cond cond, bool S, Reg d, Reg a, Reg m, Reg n); + bool arm_MLS(Cond cond, Reg d, Reg a, Reg m, Reg n); bool arm_MUL(Cond cond, bool S, Reg d, Reg m, Reg n); // Multiply (Long) instructions diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index c2044765..a0ae4cfa 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -848,6 +848,7 @@ TEST_CASE("Fuzz ARM multiply instructions", "[JitX64][A32]") { const std::array instructions = { InstructionGenerator("cccc0000001Sddddaaaammmm1001nnnn", validate_d_a_m_n), // MLA + InstructionGenerator("cccc00000110ddddaaaammmm1001nnnn", validate_d_a_m_n), // MLS InstructionGenerator("cccc0000000Sdddd0000mmmm1001nnnn", validate_d_m_n), // MUL InstructionGenerator("cccc0000111Sddddaaaammmm1001nnnn", validate_h_l_m_n), // SMLAL