backend/a64: implememnt CheckBit
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@ -551,6 +551,12 @@ void A32EmitA64::EmitA32SetZFlag(A32EmitContext& ctx, IR::Inst* inst) {
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code.STR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, CPSR_nzcv));
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}
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void A32EmitA64::EmitA32SetCheckBit(A32EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const ARM64Reg to_store = DecodeReg(ctx.reg_alloc.UseGpr(args[0]));
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code.STRB(INDEX_UNSIGNED, to_store, X28, offsetof(A32JitState, check_bit));
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}
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void A32EmitA64::EmitA32GetCFlag(A32EmitContext& ctx, IR::Inst* inst) {
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Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.ScratchGpr());
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code.LDR(INDEX_UNSIGNED, result, X28, offsetof(A32JitState, CPSR_nzcv));
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@ -1355,8 +1361,13 @@ void A32EmitA64::EmitTerminalImpl(IR::Term::If terminal, IR::LocationDescriptor
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EmitTerminal(terminal.then_, initial_location);
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}
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void A32EmitA64::EmitTerminalImpl(IR::Term::CheckBit, IR::LocationDescriptor) {
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ASSERT_MSG(false, "Term::CheckBit should never be emitted by the A32 frontend");
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void A32EmitA64::EmitTerminalImpl(IR::Term::CheckBit terminal, IR::LocationDescriptor initial_location) {
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FixupBranch fail;
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code.LDRB(INDEX_UNSIGNED, DecodeReg(code.ABI_SCRATCH1), X28, offsetof(A32JitState, check_bit));
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fail = code.CBZ(DecodeReg(code.ABI_SCRATCH1));
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EmitTerminal(terminal.then_, initial_location);
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code.SetJumpTarget(fail);
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EmitTerminal(terminal.else_, initial_location);
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}
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void A32EmitA64::EmitTerminalImpl(IR::Term::CheckHalt terminal, IR::LocationDescriptor initial_location) {
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@ -51,6 +51,7 @@ struct A32JitState {
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s64 cycles_to_run = 0;
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s64 cycles_remaining = 0;
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bool halt_requested = false;
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bool check_bit = false;
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// Exclusive state
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static constexpr u32 RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
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@ -5,6 +5,7 @@ OPCODE(Identity, Opaque, Opaq
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OPCODE(Breakpoint, Void, )
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// A32 Context getters/setters
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A32OPC(SetCheckBit, Void, U1 )
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A32OPC(GetRegister, U32, A32Reg )
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A32OPC(GetExtendedRegister32, U32, A32ExtReg )
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A32OPC(GetExtendedRegister64, U64, A32ExtReg )
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