a64_emitter: More style cleanup
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@ -324,7 +324,7 @@ void ARM64XEmitter::FlushIcache() {
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m_lastCacheFlushEnd = m_code;
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}
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void ARM64XEmitter::FlushIcacheSection(u8* start, u8* end) {
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void ARM64XEmitter::FlushIcacheSection(const u8* start, const u8* end) {
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if (start == end)
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return;
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@ -748,6 +748,8 @@ void ARM64XEmitter::EncodeBitfieldMOVInst(u32 op, ARM64Reg Rd, ARM64Reg Rn, u32
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void ARM64XEmitter::EncodeLoadStoreRegisterOffset(u32 size, u32 opc, ARM64Reg Rt, ARM64Reg Rn,
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ArithOption Rm) {
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ASSERT_MSG(Rm.GetType() == ArithOption::TYPE_EXTENDEDREG, "Shifted registers are not supported used Indexed registers");
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Rt = DecodeReg(Rt);
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Rn = DecodeReg(Rn);
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ARM64Reg decoded_Rm = DecodeReg(Rm.GetReg());
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@ -995,7 +997,7 @@ void ARM64XEmitter::BL(const void* ptr) {
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EncodeUnconditionalBranchInst(1, ptr);
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}
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void ARM64XEmitter::QuickCallFunction(ARM64Reg scratchreg, const void* func) {
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void ARM64XEmitter::QuickCallFunction(const void* func, ARM64Reg scratchreg) {
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s64 distance = reinterpret_cast<s64>(func) - reinterpret_cast<s64>(m_code);
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distance >>= 2; // Can only branch to opcode-aligned (4) addresses
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if (!IsInRangeImm26(distance)) {
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@ -444,7 +444,7 @@ public:
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return (m_shifttype << 22) | (m_shift << 10);
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break;
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default:
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DEBUG_ASSERT_MSG(false, "Invalid type in GetData");
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ASSERT_MSG(false, "Invalid type in GetData");
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break;
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}
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return 0;
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@ -512,7 +512,7 @@ public:
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const u8* AlignCodePage();
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const u8* GetCodePtr() const;
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void FlushIcache();
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void FlushIcacheSection(u8* start, u8* end);
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void FlushIcacheSection(const u8* start, const u8* end);
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u8* GetWritableCodePtr();
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// FixupBranch branching
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@ -879,10 +879,10 @@ public:
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}
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// Plain function call
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void QuickCallFunction(ARM64Reg scratchreg, const void* func);
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void QuickCallFunction(const void* func, ARM64Reg scratchreg = X16);
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template <typename T>
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void QuickCallFunction(ARM64Reg scratchreg, T func) {
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QuickCallFunction(scratchreg, (const void*)func);
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void QuickCallFunction(T func, ARM64Reg scratchreg = X16) {
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QuickCallFunction((const void*)func, scratchreg);
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}
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};
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