Squashed 'externals/xbyak/' changes from f72646a7..4a6fac8a
4a6fac8a update version to 5.77 801cf3fd cosmetic change of getNumCores d397e824 fix number of cores that share LLC cache a669e092 support non-intel-cpu visual studio af5f422e Merge branch 'fenghaitao-guard_x86' into develop 9b98dc17 Guard x86 specific codes with "#if defined(__i386__) || defined(__x86_64__)" dd4173e1 move some member variables input private git-subtree-dir: externals/xbyak git-subtree-split: 4a6fac8ade404f667b94170f713367fe7da2a852
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@ -1,5 +1,5 @@
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# Xbyak 5.76 ; JIT assembler for x86(IA32), x64(AMD64, x86-64) by C++
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# Xbyak 5.77 ; JIT assembler for x86(IA32), x64(AMD64, x86-64) by C++
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## Abstract
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@ -392,6 +392,7 @@ modified new BSD License
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http://opensource.org/licenses/BSD-3-Clause
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## History
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* 2019/Mar/06 ver 5.77 fix number of cores that share LLC cache by densamoilov
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* 2019/Jan/17 ver 5.76 add Cpu::getNumCores() by shelleygoel
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* 2018/Oct/31 ver 5.751 recover Xbyak::CastTo for compatibility
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* 2018/Oct/29 ver 5.75 unlink LabelManager from Label when msg is destroyed
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@ -1,5 +1,5 @@
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C++用x86(IA-32), x64(AMD64, x86-64) JITアセンブラ Xbyak 5.76
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C++用x86(IA-32), x64(AMD64, x86-64) JITアセンブラ Xbyak 5.77
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-----------------------------------------------------------------------------
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◎概要
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@ -373,6 +373,7 @@ sample/{echo,hello}.bfは http://www.kmonos.net/alang/etc/brainfuck.php から
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-----------------------------------------------------------------------------
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◎履歴
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2019/03/06 ver 5.77 LLCキャッシュを共有数CPU数の修整(by densamoilov)
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2019/01/17 ver 5.76 Cpu::getNumCores()追加(by shelleygoel)
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2018/10/31 ver 5.751 互換性のためにXbyak::CastToの復元
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2018/10/29 ver 5.75 LabelManagerのデストラクタでLabelから参照を切り離す
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@ -113,7 +113,7 @@ namespace Xbyak {
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enum {
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DEFAULT_MAX_CODE_SIZE = 4096,
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VERSION = 0x5760 /* 0xABCD = A.BC(D) */
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VERSION = 0x5770 /* 0xABCD = A.BC(D) */
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};
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#ifndef MIE_INTEGER_TYPE_DEFINED
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@ -1,4 +1,4 @@
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const char *getVersionString() const { return "5.76"; }
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const char *getVersionString() const { return "5.77"; }
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void adc(const Operand& op, uint32 imm) { opRM_I(op, imm, 0x10, 2); }
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void adc(const Operand& op1, const Operand& op2) { opRM_RM(op1, op2, 0x10); }
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void adcx(const Reg32e& reg, const Operand& op) { opGen(reg, op, 0xF6, 0x66, isREG32_REG32orMEM, NONE, 0x38); }
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@ -9,6 +9,11 @@
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*/
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#include "xbyak.h"
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#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
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#define XBYAK_INTEL_CPU_SPECIFIC
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#endif
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#ifdef XBYAK_INTEL_CPU_SPECIFIC
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#ifdef _MSC_VER
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#if (_MSC_VER < 1400) && defined(XBYAK32)
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static inline __declspec(naked) void __cpuid(int[4], int)
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@ -47,6 +52,7 @@
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#endif
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#endif
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#endif
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#endif
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namespace Xbyak { namespace util {
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@ -65,6 +71,11 @@ class Cpu {
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static const size_t maxTopologyLevels = 2;
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unsigned int numCores_[maxTopologyLevels];
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static const unsigned int maxNumberCacheLevels = 10;
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unsigned int dataCacheSize_[maxNumberCacheLevels];
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unsigned int coresSharignDataCache_[maxNumberCacheLevels];
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unsigned int dataCacheLevels_;
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unsigned int get32bitAsBE(const char *x) const
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{
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return x[0] | (x[1] << 8) | (x[2] << 16) | (x[3] << 24);
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@ -75,7 +86,7 @@ class Cpu {
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}
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void setFamily()
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{
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unsigned int data[4];
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unsigned int data[4] = {};
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getCpuid(1, data);
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stepping = data[0] & mask(4);
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model = (data[0] >> 4) & mask(4);
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@ -102,7 +113,7 @@ class Cpu {
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{
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if ((type_ & tINTEL) == 0) return;
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unsigned int data[4];
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unsigned int data[4] = {};
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/* CAUTION: These numbers are configuration as shipped by Intel. */
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getCpuidEx(0x0, 0, data);
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@ -121,9 +132,6 @@ class Cpu {
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numCores_[level - 1] = extractBit(data[1], 0, 15);
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}
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}
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if (numCores_[SmtLevel - 1] != 0) {
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numCores_[CoreLevel - 1] /= numCores_[SmtLevel - 1];
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}
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} else {
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/*
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Failed to deremine num of cores without x2APIC support.
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@ -143,7 +151,7 @@ class Cpu {
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const unsigned int UNIFIED_CACHE = 3;
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unsigned int smt_width = 0;
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unsigned int logical_cores = 0;
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unsigned int data[4];
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unsigned int data[4] = {};
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if (x2APIC_supported_) {
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smt_width = numCores_[0];
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@ -159,7 +167,7 @@ class Cpu {
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on socket reported by leaf 11, then it is a correct number
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of cores not an upperbound.
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*/
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for (int i = 0; data_cache_levels < maxNumberCacheLevels; i++) {
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for (int i = 0; dataCacheLevels_ < maxNumberCacheLevels; i++) {
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getCpuidEx(0x4, i, data);
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unsigned int cacheType = extractBit(data[0], 0, 4);
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if (cacheType == NO_CACHE) break;
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@ -169,15 +177,15 @@ class Cpu {
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actual_logical_cores = (std::min)(actual_logical_cores, logical_cores);
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}
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assert(actual_logical_cores != 0);
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data_cache_size[data_cache_levels] =
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dataCacheSize_[dataCacheLevels_] =
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(extractBit(data[1], 22, 31) + 1)
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* (extractBit(data[1], 12, 21) + 1)
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* (extractBit(data[1], 0, 11) + 1)
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* (data[2] + 1);
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if (cacheType == DATA_CACHE && smt_width == 0) smt_width = actual_logical_cores;
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assert(smt_width != 0);
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cores_sharing_data_cache[data_cache_levels] = (std::max)(actual_logical_cores / smt_width, 1u);
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data_cache_levels++;
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coresSharignDataCache_[dataCacheLevels_] = (std::max)(actual_logical_cores / smt_width, 1u);
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dataCacheLevels_++;
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}
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}
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}
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@ -191,28 +199,25 @@ public:
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int displayFamily; // family + extFamily
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int displayModel; // model + extModel
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// may I move these members into private?
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static const unsigned int maxNumberCacheLevels = 10;
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unsigned int data_cache_size[maxNumberCacheLevels];
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unsigned int cores_sharing_data_cache[maxNumberCacheLevels];
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unsigned int data_cache_levels;
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unsigned int getNumCores(IntelCpuTopologyLevel level) {
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if (level != SmtLevel && level != CoreLevel) throw Error(ERR_BAD_PARAMETER);
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if (!x2APIC_supported_) throw Error(ERR_X2APIC_IS_NOT_SUPPORTED);
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return numCores_[level - 1];
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switch (level) {
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case SmtLevel: return numCores_[level - 1];
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case CoreLevel: return numCores_[level - 1] / numCores_[SmtLevel - 1];
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default: throw Error(ERR_X2APIC_IS_NOT_SUPPORTED);
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}
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}
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unsigned int getDataCacheLevels() const { return data_cache_levels; }
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unsigned int getDataCacheLevels() const { return dataCacheLevels_; }
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unsigned int getCoresSharingDataCache(unsigned int i) const
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{
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if (i >= data_cache_levels) throw Error(ERR_BAD_PARAMETER);
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return cores_sharing_data_cache[i];
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if (i >= dataCacheLevels_) throw Error(ERR_BAD_PARAMETER);
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return coresSharignDataCache_[i];
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}
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unsigned int getDataCacheSize(unsigned int i) const
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{
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if (i >= data_cache_levels) throw Error(ERR_BAD_PARAMETER);
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return data_cache_size[i];
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if (i >= dataCacheLevels_) throw Error(ERR_BAD_PARAMETER);
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return dataCacheSize_[i];
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}
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/*
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*/
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static inline void getCpuid(unsigned int eaxIn, unsigned int data[4])
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{
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#ifdef _MSC_VER
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#ifdef XBYAK_INTEL_CPU_SPECIFIC
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#ifdef _MSC_VER
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__cpuid(reinterpret_cast<int*>(data), eaxIn);
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#else
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#else
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__cpuid(eaxIn, data[0], data[1], data[2], data[3]);
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#endif
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#else
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(void)eaxIn;
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(void)data;
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#endif
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}
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static inline void getCpuidEx(unsigned int eaxIn, unsigned int ecxIn, unsigned int data[4])
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{
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#ifdef _MSC_VER
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#ifdef XBYAK_INTEL_CPU_SPECIFIC
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#ifdef _MSC_VER
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__cpuidex(reinterpret_cast<int*>(data), eaxIn, ecxIn);
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#else
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#else
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__cpuid_count(eaxIn, ecxIn, data[0], data[1], data[2], data[3]);
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#endif
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#else
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(void)eaxIn;
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(void)ecxIn;
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(void)data;
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#endif
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}
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static inline uint64 getXfeature()
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{
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#ifdef _MSC_VER
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#ifdef XBYAK_INTEL_CPU_SPECIFIC
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#ifdef _MSC_VER
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return _xgetbv(0);
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#else
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#else
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unsigned int eax, edx;
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// xgetvb is not support on gcc 4.2
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// __asm__ volatile("xgetbv" : "=a"(eax), "=d"(edx) : "c"(0));
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__asm__ volatile(".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(0));
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return ((uint64)edx << 32) | eax;
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#endif
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#else
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return 0;
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#endif
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}
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typedef uint64 Type;
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: type_(NONE)
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, x2APIC_supported_(false)
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, numCores_()
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, data_cache_levels(0)
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, dataCacheSize_()
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, coresSharignDataCache_()
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, dataCacheLevels_(0)
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{
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unsigned int data[4];
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unsigned int data[4] = {};
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const unsigned int& EAX = data[0];
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const unsigned int& EBX = data[1];
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const unsigned int& ECX = data[2];
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public:
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static inline uint64 getRdtsc()
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{
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#ifdef _MSC_VER
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#ifdef XBYAK_INTEL_CPU_SPECIFIC
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#ifdef _MSC_VER
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return __rdtsc();
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#else
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#else
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unsigned int eax, edx;
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__asm__ volatile("rdtsc" : "=a"(eax), "=d"(edx));
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return ((uint64)edx << 32) | eax;
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#endif
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#else
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// TODO: Need another impl of Clock or rdtsc-equivalent for non-x86 cpu
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return 0;
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#endif
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}
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Clock()
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