diff --git a/src/backend/x64/emit_x64_floating_point.cpp b/src/backend/x64/emit_x64_floating_point.cpp
index 43135eab..c9094dc5 100644
--- a/src/backend/x64/emit_x64_floating_point.cpp
+++ b/src/backend/x64/emit_x64_floating_point.cpp
@@ -754,6 +754,10 @@ static void EmitFPRecipEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* i
     code.CallFunction(&FP::FPRecipEstimate<FPT>);
 }
 
+void EmitX64::EmitFPRecipEstimate16(EmitContext& ctx, IR::Inst* inst) {
+    EmitFPRecipEstimate<u16>(code, ctx, inst);
+}
+
 void EmitX64::EmitFPRecipEstimate32(EmitContext& ctx, IR::Inst* inst) {
     EmitFPRecipEstimate<u32>(code, ctx, inst);
 }
diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp
index ea2d509a..a421ff29 100644
--- a/src/frontend/ir/ir_emitter.cpp
+++ b/src/frontend/ir/ir_emitter.cpp
@@ -1922,11 +1922,18 @@ U16U32U64 IREmitter::FPNeg(const U16U32U64& a) {
     }
 }
 
-U32U64 IREmitter::FPRecipEstimate(const U32U64& a) {
-    if (a.GetType() == Type::U32) {
+U16U32U64 IREmitter::FPRecipEstimate(const U16U32U64& a) {
+    switch (a.GetType()) {
+    case Type::U16:
+        return Inst<U16>(Opcode::FPRecipEstimate16, a);
+    case Type::U32:
         return Inst<U32>(Opcode::FPRecipEstimate32, a);
+    case Type::U64:
+        return Inst<U64>(Opcode::FPRecipEstimate64, a);
+    default:
+        UNREACHABLE();
+        return U16U32U64{};
     }
-    return Inst<U64>(Opcode::FPRecipEstimate64, a);
 }
 
 U16U32U64 IREmitter::FPRecipExponent(const U16U32U64& a) {
diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h
index 5f6d32fc..e181a11c 100644
--- a/src/frontend/ir/ir_emitter.h
+++ b/src/frontend/ir/ir_emitter.h
@@ -305,7 +305,7 @@ public:
     U16U32U64 FPMulAdd(const U16U32U64& addend, const U16U32U64& op1, const U16U32U64& op2, bool fpcr_controlled);
     U32U64 FPMulX(const U32U64& a, const U32U64& b);
     U16U32U64 FPNeg(const U16U32U64& a);
-    U32U64 FPRecipEstimate(const U32U64& a);
+    U16U32U64 FPRecipEstimate(const U16U32U64& a);
     U16U32U64 FPRecipExponent(const U16U32U64& a);
     U16U32U64 FPRecipStepFused(const U16U32U64& a, const U16U32U64& b);
     U16U32U64 FPRoundInt(const U16U32U64& a, FP::RoundingMode rounding, bool exact);
diff --git a/src/frontend/ir/microinstruction.cpp b/src/frontend/ir/microinstruction.cpp
index 873727a6..8a2d49d8 100644
--- a/src/frontend/ir/microinstruction.cpp
+++ b/src/frontend/ir/microinstruction.cpp
@@ -272,6 +272,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
     case Opcode::FPMulAdd16:
     case Opcode::FPMulAdd32:
     case Opcode::FPMulAdd64:
+    case Opcode::FPRecipEstimate16:
     case Opcode::FPRecipEstimate32:
     case Opcode::FPRecipEstimate64:
     case Opcode::FPRecipExponent16:
diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc
index dcfcf1a8..07fe9ca4 100644
--- a/src/frontend/ir/opcodes.inc
+++ b/src/frontend/ir/opcodes.inc
@@ -491,6 +491,7 @@ OPCODE(FPMulX64,                                            U64,            U64,
 OPCODE(FPNeg16,                                             U16,            U16                                                             )
 OPCODE(FPNeg32,                                             U32,            U32                                                             )
 OPCODE(FPNeg64,                                             U64,            U64                                                             )
+OPCODE(FPRecipEstimate16,                                   U16,            U16                                                             )
 OPCODE(FPRecipEstimate32,                                   U32,            U32                                                             )
 OPCODE(FPRecipEstimate64,                                   U64,            U64                                                             )
 OPCODE(FPRecipExponent16,                                   U16,            U16                                                             )