From 2e0fcd6161d0ce019851e81adfd770dcfb6ddab4 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sun, 16 Sep 2018 18:41:01 -0400 Subject: [PATCH] A64: Implement CLS's vector variant Leverages CLZ like the integral variant does. --- src/frontend/A64/decoder/a64.inc | 2 +- .../translate/impl/simd_two_register_misc.cpp | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 4dc3e619..bb42f89b 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -567,7 +567,7 @@ INST(REV64_asimd, "REV64", "0Q001 INST(REV16_asimd, "REV16 (vector)", "0Q001110zz100000000110nnnnnddddd") INST(SADDLP, "SADDLP", "0Q001110zz100000001010nnnnnddddd") INST(SUQADD_2, "SUQADD", "0Q001110zz100000001110nnnnnddddd") -//INST(CLS_asimd, "CLS (vector)", "0Q001110zz100000010010nnnnnddddd") +INST(CLS_asimd, "CLS (vector)", "0Q001110zz100000010010nnnnnddddd") INST(CNT, "CNT", "0Q001110zz100000010110nnnnnddddd") INST(SADALP, "SADALP", "0Q001110zz100000011010nnnnnddddd") INST(SQABS_2, "SQABS", "0Q001110zz100000011110nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp index 6cf3bda4..d59c9b24 100644 --- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp @@ -193,6 +193,28 @@ bool PairedAddLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Si } // Anonymous namespace +bool TranslatorVisitor::CLS_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) { + if (size == 0b11) { + return ReservedValue(); + } + + const size_t esize = 8 << size.ZeroExtend(); + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand = V(datasize, Vn); + const IR::U128 shifted = ir.VectorArithmeticShiftRight(esize, operand, static_cast(esize)); + const IR::U128 xored = ir.VectorEor(operand, shifted); + const IR::U128 clz = ir.VectorCountLeadingZeros(esize, xored); + IR::U128 result = ir.VectorSub(esize, clz, ir.VectorBroadcast(esize, I(esize, 1))); + + if (datasize == 64) { + result = ir.VectorZeroUpper(result); + } + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::CLZ_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) { if (size == 0b11) { return ReservedValue();