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backend\A64\emit_a64_data_processing.cpp: Implement Division

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SachinVin 2019-07-21 12:26:41 +05:30 committed by xperia64
parent 374c703335
commit 2f9f317c9e
4 changed files with 48 additions and 7 deletions
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42
src/backend/A64/emit_a64_data_processing.cpp
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@ -896,6 +896,48 @@ void EmitA64::EmitMul64(EmitContext& ctx, IR::Inst* inst) {
ctx.reg_alloc.DefineValue(inst, result);
}
void EmitA64::EmitUnsignedDiv32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(args[0]));
const ARM64Reg divisor = DecodeReg(ctx.reg_alloc.UseGpr(args[1]));
code.UDIV(result, result, divisor);
ctx.reg_alloc.DefineValue(inst, result);
}
void EmitA64::EmitUnsignedDiv64(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const ARM64Reg result = ctx.reg_alloc.UseScratchGpr(args[0]);
const ARM64Reg divisor = ctx.reg_alloc.UseGpr(args[1]);
code.UDIV(result, result, divisor);
ctx.reg_alloc.DefineValue(inst, result);
}
void EmitA64::EmitSignedDiv32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(args[0]));
const ARM64Reg divisor = DecodeReg(ctx.reg_alloc.UseGpr(args[1]));
code.SDIV(result, result, divisor);
ctx.reg_alloc.DefineValue(inst, result);
}
void EmitA64::EmitSignedDiv64(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const ARM64Reg result = ctx.reg_alloc.UseScratchGpr(args[0]);
const ARM64Reg divisor = ctx.reg_alloc.UseGpr(args[1]);
code.SDIV(result, result, divisor);
ctx.reg_alloc.DefineValue(inst, result);
}
void EmitA64::EmitAnd32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);

1
src/backend/A64/emit_a64_floating_point.cpp
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@ -286,7 +286,6 @@ void FPThreeOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn)
result = fsize == 32 ? EncodeRegToSingle(result) : EncodeRegToDouble(result);
operand = fsize == 32 ? EncodeRegToSingle(operand) : EncodeRegToDouble(operand);
if constexpr (std::is_member_function_pointer_v<Function>) {
(code.fp_emitter.*fn)(result, result, operand);
}

8
src/backend/A64/opcodes.inc
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@ -118,10 +118,10 @@ OPCODE(Mul32, U32, U32,
OPCODE(Mul64, U64, U64, U64 )
//OPCODE(SignedMultiplyHigh64, U64, U64, U64 )
//OPCODE(UnsignedMultiplyHigh64, U64, U64, U64 )
//OPCODE(UnsignedDiv32, U32, U32, U32 )
//OPCODE(UnsignedDiv64, U64, U64, U64 )
//OPCODE(SignedDiv32, U32, U32, U32 )
//OPCODE(SignedDiv64, U64, U64, U64 )
OPCODE(UnsignedDiv32, U32, U32, U32 )
OPCODE(UnsignedDiv64, U64, U64, U64 )
OPCODE(SignedDiv32, U32, U32, U32 )
OPCODE(SignedDiv64, U64, U64, U64 )
OPCODE(And32, U32, U32, U32 )
OPCODE(And64, U64, U64, U64 )
OPCODE(Eor32, U32, U32, U32 )

4
src/frontend/A32/decoder/arm_a64.inc
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@ -206,8 +206,8 @@ INST(arm_REVSH, "REVSH", "cccc011011111111dddd11111011mmmm
//INST(arm_USAT16, "USAT16", "cccc01101110vvvvdddd11110011nnnn") // v6
// Divide instructions
//INST(arm_SDIV, "SDIV", "cccc01110001dddd1111mmmm0001nnnn") // v7a
//INST(arm_UDIV, "UDIV", "cccc01110011dddd1111mmmm0001nnnn") // v7a
INST(arm_SDIV, "SDIV", "cccc01110001dddd1111mmmm0001nnnn") // v7a
INST(arm_UDIV, "UDIV", "cccc01110011dddd1111mmmm0001nnnn") // v7a
// Multiply (Normal) instructions
INST(arm_MLA, "MLA", "cccc0000001Sddddaaaammmm1001nnnn") // v2