From 33b3376fb19dfe03858abe0550da7e621d806df4 Mon Sep 17 00:00:00 2001
From: Merry <git@mary.rs>
Date: Sat, 30 Jul 2022 19:10:35 +0100
Subject: [PATCH] emit_arm64_a32: Implement A32SetCpsrNZCVRaw, A32SetCpsrNZCVQ

---
 src/dynarmic/backend/arm64/emit_arm64_a32.cpp | 22 ++++++++++++-------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/src/dynarmic/backend/arm64/emit_arm64_a32.cpp b/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
index 47094060..2a68d9b0 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
@@ -274,18 +274,24 @@ void EmitIR<IR::Opcode::A32SetCpsrNZCV>(oaknut::CodeGenerator& code, EmitContext
 
 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZCVRaw>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
+    auto Wnzcv = ctx.reg_alloc.ReadW(args[0]);
+    RegAlloc::Realize(Wnzcv);
+
+    code.STR(Wnzcv, Xstate, offsetof(A32JitState, cpsr_nzcv));
 }
 
 template<>
 void EmitIR<IR::Opcode::A32SetCpsrNZCVQ>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
+    auto Wnzcv = ctx.reg_alloc.ReadW(args[0]);
+    RegAlloc::Realize(Wnzcv);
+
+    static_assert(offsetof(A32JitState, cpsr_nzcv) + sizeof(u32) == offsetof(A32JitState, cpsr_q));
+
+    code.AND(Wscratch0, Wnzcv, 0xf000'0000);
+    code.AND(Wscratch1, Wnzcv, 0x0800'0000);
+    code.STP(Wscratch0, Wscratch1, Xstate, offsetof(A32JitState, cpsr_nzcv));
 }
 
 template<>