diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index 9b349461..1a6fc7ff 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -324,7 +324,6 @@ INST(AESIMC,                 "AESIMC",                                    "01001
 
 // Data Processing - FP and SIMD - Scalar copy
 //INST(DUP_elt_1,              "DUP (element)",                             "01011110000iiiii000001nnnnnddddd")
-//INST(DUP_elt_2,              "DUP (element)",                             "0Q001110000iiiii000001nnnnnddddd")
 
 // Data Processing - FP and SIMD - Scalar three
 //INST(FMULX_vec_1,            "FMULX",                                     "01011110010mmmmm000111nnnnnddddd")
@@ -568,6 +567,7 @@ INST(ZIP1,                   "ZIP1",                                      "0Q001
 //INST(EXT,                    "EXT",                                       "0Q101110000mmmmm0iiii0nnnnnddddd")
 
 // Data Processing - FP and SIMD - SIMD Copy
+INST(DUP_elt_2,              "DUP (element)",                             "0Q001110000iiiii000001nnnnnddddd")
 INST(DUP_gen,                "DUP (general)",                             "0Q001110000iiiii000011nnnnnddddd")
 INST(SMOV,                   "SMOV",                                      "0Q001110000iiiii001011nnnnnddddd")
 INST(UMOV,                   "UMOV",                                      "0Q001110000iiiii001111nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/impl.h b/src/frontend/A64/translate/impl/impl.h
index 8419d095..3dfbbe81 100644
--- a/src/frontend/A64/translate/impl/impl.h
+++ b/src/frontend/A64/translate/impl/impl.h
@@ -386,7 +386,6 @@ struct TranslatorVisitor final {
 
     // Data Processing - FP and SIMD - Scalar copy
     bool DUP_elt_1(Imm<5> imm5, Vec Vn, Vec Vd);
-    bool DUP_elt_2(bool Q, Imm<5> imm5, Vec Vn, Vec Vd);
 
     // Data Processing - FP and SIMD - Scalar three
     bool FMULX_vec_1(Vec Vm, Vec Vn, Vec Vd);
@@ -685,6 +684,7 @@ struct TranslatorVisitor final {
     bool EXT(bool Q, Vec Vm, Imm<4> imm4, Vec Vn, Vec Vd);
 
     // Data Processing - FP and SIMD - SIMD Copy
+    bool DUP_elt_2(bool Q, Imm<5> imm5, Vec Vn, Vec Vd);
     bool DUP_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd);
     bool SMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd);
     bool UMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd);
diff --git a/src/frontend/A64/translate/impl/simd_copy.cpp b/src/frontend/A64/translate/impl/simd_copy.cpp
index 18c5d037..17d98d9b 100644
--- a/src/frontend/A64/translate/impl/simd_copy.cpp
+++ b/src/frontend/A64/translate/impl/simd_copy.cpp
@@ -9,6 +9,23 @@
 
 namespace Dynarmic::A64 {
 
+bool TranslatorVisitor::DUP_elt_2(bool Q, Imm<5> imm5, Vec Vn, Vec Vd) {
+    const size_t size = Common::LowestSetBit(imm5.ZeroExtend());
+    if (size > 3) return UnallocatedEncoding();
+    if (size == 3 && !Q) return ReservedValue();
+
+    const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1);
+    const size_t idxdsize = imm5.Bit<4>() ? 128 : 64;
+    const size_t esize = 8 << size;
+    const size_t datasize = Q ? 128 : 64;
+
+    const IR::U128 operand = V(idxdsize, Vn);
+    const IR::UAny element = ir.VectorGetElement(esize, operand, index);
+    const IR::U128 result = Q ? ir.VectorBroadcast(esize, element) : ir.VectorBroadcastLower(esize, element);
+    V(datasize, Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::DUP_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd) {
     const size_t size = Common::LowestSetBit(imm5.ZeroExtend());
     if (size > 3) return UnallocatedEncoding();