From 3a50d444dcb66c868528dd12057f63dc623d09a5 Mon Sep 17 00:00:00 2001
From: MerryMage <MerryMage@users.noreply.github.com>
Date: Thu, 28 May 2020 21:53:50 +0100
Subject: [PATCH] A32: Implement ASIMD VHSUB
---
src/frontend/A32/decoder/asimd.inc | 2 +-
.../A32/translate/impl/asimd_three_same.cpp | 23 +++++++++++++++++++
.../A32/translate/impl/translate_arm.h | 1 +
3 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc
index 9b8b1156..469571b6 100644
--- a/src/frontend/A32/decoder/asimd.inc
+++ b/src/frontend/A32/decoder/asimd.inc
@@ -10,7 +10,7 @@ INST(asimd_VEOR_reg, "VEOR (register)", "111100110D00nnnndddd000
INST(asimd_VBSL, "VBSL", "111100110D01nnnndddd0001NQM1mmmm") // ASIMD
INST(asimd_VBIT, "VBIT", "111100110D10nnnndddd0001NQM1mmmm") // ASIMD
INST(asimd_VBIF, "VBIF", "111100110D11nnnndddd0001NQM1mmmm") // ASIMD
-//INST(asimd_VHADD, "VHADD", "1111001U0-CC--------0010---0----") // ASIMD
+INST(asimd_VHSUB, "VHSUB", "1111001U0Dzznnnndddd0010NQM0mmmm") // ASIMD
//INST(asimd_VQSUB, "VQSUB", "1111001U0-CC--------0010---1----") // ASIMD
//INST(asimd_VCGT_reg, "VCGT (register)", "1111001U0-CC--------0011---0----") // ASIMD
//INST(asimd_VCGE_reg, "VCGE (register)", "1111001U0-CC--------0011---1----") // ASIMD
diff --git a/src/frontend/A32/translate/impl/asimd_three_same.cpp b/src/frontend/A32/translate/impl/asimd_three_same.cpp
index 314a8466..687727ef 100644
--- a/src/frontend/A32/translate/impl/asimd_three_same.cpp
+++ b/src/frontend/A32/translate/impl/asimd_three_same.cpp
@@ -127,4 +127,27 @@ bool ArmTranslatorVisitor::asimd_VBIF(bool D, size_t Vn, size_t Vd, bool N, bool
return ir.VectorOr(ir.VectorAnd(reg_d, reg_m), ir.VectorAnd(reg_n, ir.VectorNot(reg_m)));
});
}
+
+bool ArmTranslatorVisitor::asimd_VHSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
+ if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
+ return UndefinedInstruction();
+ }
+
+ if (sz == 0b11) {
+ return UndefinedInstruction();
+ }
+
+ const size_t esize = 8 << sz;
+ const auto d = ToVector(Q, Vd, D);
+ const auto m = ToVector(Q, Vm, M);
+ const auto n = ToVector(Q, Vn, N);
+
+ const IR::U128 reg_n = ir.GetVector(n);
+ const IR::U128 reg_m = ir.GetVector(m);
+ const IR::U128 result = U ? ir.VectorHalvingSubUnsigned(esize, reg_n, reg_m) : ir.VectorHalvingSubSigned(esize, reg_n, reg_m);
+ ir.SetVector(d, result);
+
+ return true;
+}
+
} // namespace Dynarmic::A32
diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h
index bde2d7a3..88014631 100644
--- a/src/frontend/A32/translate/impl/translate_arm.h
+++ b/src/frontend/A32/translate/impl/translate_arm.h
@@ -444,6 +444,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VBSL(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VBIT(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VBIF(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
+ bool asimd_VHSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
// Advanced SIMD two register, miscellaneous
bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm);