From 3c00a616d6faf9f35c3f4970c09566b7d3bbf300 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Fri, 1 Mar 2019 01:23:48 -0500 Subject: [PATCH] translate_arm/packing: Invert conditionals where applicable --- .../A32/translate/translate_arm/packing.cpp | 36 +++++++++++-------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/src/frontend/A32/translate/translate_arm/packing.cpp b/src/frontend/A32/translate/translate_arm/packing.cpp index a0e10288..6ebb5672 100644 --- a/src/frontend/A32/translate/translate_arm/packing.cpp +++ b/src/frontend/A32/translate/translate_arm/packing.cpp @@ -8,31 +8,39 @@ namespace Dynarmic::A32 { +// PKHBT , , {, LSL #} bool ArmTranslatorVisitor::arm_PKHBT(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) { - if (n == Reg::PC || d == Reg::PC || m == Reg::PC) + if (n == Reg::PC || d == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); - - if (ConditionPassed(cond)) { - auto shifted = EmitImmShift(ir.GetRegister(m), ShiftType::LSL, imm5, ir.Imm1(false)).result; - auto lower_half = ir.And(ir.GetRegister(n), ir.Imm32(0x0000FFFF)); - auto upper_half = ir.And(shifted, ir.Imm32(0xFFFF0000)); - ir.SetRegister(d, ir.Or(lower_half, upper_half)); } + if (!ConditionPassed(cond)) { + return true; + } + + const auto shifted = EmitImmShift(ir.GetRegister(m), ShiftType::LSL, imm5, ir.Imm1(false)).result; + const auto lower_half = ir.And(ir.GetRegister(n), ir.Imm32(0x0000FFFF)); + const auto upper_half = ir.And(shifted, ir.Imm32(0xFFFF0000)); + + ir.SetRegister(d, ir.Or(lower_half, upper_half)); return true; } +// PKHTB , , {, ASR #} bool ArmTranslatorVisitor::arm_PKHTB(Cond cond, Reg n, Reg d, Imm5 imm5, Reg m) { - if (n == Reg::PC || d == Reg::PC || m == Reg::PC) + if (n == Reg::PC || d == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); - - if (ConditionPassed(cond)) { - auto shifted = EmitImmShift(ir.GetRegister(m), ShiftType::ASR, imm5, ir.Imm1(false)).result; - auto lower_half = ir.And(shifted, ir.Imm32(0x0000FFFF)); - auto upper_half = ir.And(ir.GetRegister(n), ir.Imm32(0xFFFF0000)); - ir.SetRegister(d, ir.Or(lower_half, upper_half)); } + if (!ConditionPassed(cond)) { + return true; + } + + const auto shifted = EmitImmShift(ir.GetRegister(m), ShiftType::ASR, imm5, ir.Imm1(false)).result; + const auto lower_half = ir.And(shifted, ir.Imm32(0x0000FFFF)); + const auto upper_half = ir.And(ir.GetRegister(n), ir.Imm32(0xFFFF0000)); + + ir.SetRegister(d, ir.Or(lower_half, upper_half)); return true; }