From 4039030234f786405360f61ce671c8cca7ecfc21 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Sun, 9 Sep 2018 17:46:21 -0400
Subject: [PATCH] A64: Implement CLZ's vector variant

---
 src/frontend/A64/decoder/a64.inc              |  2 +-
 .../translate/impl/simd_two_register_misc.cpp | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index 52528b03..b876e2e7 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -616,7 +616,7 @@ INST(FRECPE_4,               "FRECPE",                                    "0Q001
 INST(REV32_asimd,            "REV32 (vector)",                            "0Q101110zz100000000010nnnnnddddd")
 INST(UADDLP,                 "UADDLP",                                    "0Q101110zz100000001010nnnnnddddd")
 INST(USQADD_2,               "USQADD",                                    "0Q101110zz100000001110nnnnnddddd")
-//INST(CLZ_asimd,              "CLZ (vector)",                              "0Q101110zz100000010010nnnnnddddd")
+INST(CLZ_asimd,              "CLZ (vector)",                              "0Q101110zz100000010010nnnnnddddd")
 INST(UADALP,                 "UADALP",                                    "0Q101110zz100000011010nnnnnddddd")
 INST(SQNEG_2,                "SQNEG",                                     "0Q101110zz100000011110nnnnnddddd")
 INST(CMGE_zero_2,            "CMGE (zero)",                               "0Q101110zz100000100010nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
index eea1c61a..6cf3bda4 100644
--- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
+++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp
@@ -193,6 +193,25 @@ bool PairedAddLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Si
 
 } // Anonymous namespace
 
+bool TranslatorVisitor::CLZ_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
+    if (size == 0b11) {
+        return ReservedValue();
+    }
+
+    const size_t esize = 8 << size.ZeroExtend();
+    const size_t datasize = Q ? 128 : 64;
+
+    const IR::U128 operand = V(datasize, Vn);
+    IR::U128 result = ir.VectorCountLeadingZeros(esize, operand);
+
+    if (datasize == 64) {
+        result = ir.VectorZeroUpper(result);
+    }
+
+    V(datasize, Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::CNT(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
     if (size != 0b00) {
         return ReservedValue();