From 40db85e783fc19989e9b426e91e29a98d3178e67 Mon Sep 17 00:00:00 2001 From: SachinVin Date: Sat, 10 Sep 2022 13:53:05 +0530 Subject: [PATCH] backend/A64: Implement AndNot32 fix AndNot32 --- src/dynarmic/backend/A64/emit_a64_data_processing.cpp | 9 +++++++++ src/dynarmic/backend/A64/opcodes.inc | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/dynarmic/backend/A64/emit_a64_data_processing.cpp b/src/dynarmic/backend/A64/emit_a64_data_processing.cpp index aef70053..73de2edb 100644 --- a/src/dynarmic/backend/A64/emit_a64_data_processing.cpp +++ b/src/dynarmic/backend/A64/emit_a64_data_processing.cpp @@ -911,6 +911,15 @@ void EmitA64::EmitAnd64(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, result); } +void EmitA64::EmitAndNot32(EmitContext& ctx, IR::Inst* inst) { + auto args = ctx.reg_alloc.GetArgumentInfo(inst); + + Arm64Gen::ARM64Reg op_a = EncodeRegTo32(ctx.reg_alloc.UseGpr(args[0])); + Arm64Gen::ARM64Reg result = EncodeRegTo32(ctx.reg_alloc.UseScratchGpr(args[1])); + code.BIC(result, op_a, result); + ctx.reg_alloc.DefineValue(inst, result); +} + void EmitA64::EmitEor32(EmitContext& ctx, IR::Inst* inst) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); diff --git a/src/dynarmic/backend/A64/opcodes.inc b/src/dynarmic/backend/A64/opcodes.inc index 34933052..550d557c 100644 --- a/src/dynarmic/backend/A64/opcodes.inc +++ b/src/dynarmic/backend/A64/opcodes.inc @@ -136,7 +136,7 @@ OPCODE(SignedDiv32, U32, U32, OPCODE(SignedDiv64, U64, U64, U64 ) OPCODE(And32, U32, U32, U32 ) OPCODE(And64, U64, U64, U64 ) -//OPCODE(AndNot32, U32, U32, U32 ) +OPCODE(AndNot32, U32, U32, U32 ) //OPCODE(AndNot64, U64, U64, U64 ) OPCODE(Eor32, U32, U32, U32 ) OPCODE(Eor64, U64, U64, U64 )