From 462c88468558d9e71ad52fd842f25067de863983 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Tue, 4 May 2021 16:18:03 +0100 Subject: [PATCH] frontend/A32: Correct more IT state --- src/frontend/A32/translate/conditional_state.cpp | 4 ++-- src/frontend/A32/translate/impl/thumb16.cpp | 4 ++-- src/frontend/A32/translate/impl/thumb32_branch.cpp | 4 ++-- src/frontend/A32/translate/impl/thumb32_control.cpp | 4 +++- src/frontend/A32/translate/impl/vfp.cpp | 3 ++- 5 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/frontend/A32/translate/conditional_state.cpp b/src/frontend/A32/translate/conditional_state.cpp index 884a31be..e156b1c3 100644 --- a/src/frontend/A32/translate/conditional_state.cpp +++ b/src/frontend/A32/translate/conditional_state.cpp @@ -41,7 +41,7 @@ bool IsConditionPassed(TranslatorVisitor& v, IR::Cond cond) { v.cond_state = ConditionalState::Trailing; } else { if (cond == v.ir.block.GetCondition()) { - v.ir.block.SetConditionFailedLocation(v.ir.current_location.AdvancePC(v.current_instruction_size).AdvanceIT()); + v.ir.block.SetConditionFailedLocation(v.ir.current_location.AdvancePC(static_cast(v.current_instruction_size)).AdvanceIT()); v.ir.block.ConditionFailedCycleCount()++; return true; } @@ -72,7 +72,7 @@ bool IsConditionPassed(TranslatorVisitor& v, IR::Cond cond) { v.cond_state = ConditionalState::Translating; v.ir.block.SetCondition(cond); - v.ir.block.SetConditionFailedLocation(v.ir.current_location.AdvancePC(v.current_instruction_size).AdvanceIT()); + v.ir.block.SetConditionFailedLocation(v.ir.current_location.AdvancePC(static_cast(v.current_instruction_size)).AdvanceIT()); v.ir.block.ConditionFailedCycleCount() = v.ir.block.CycleCount() + 1; return true; } diff --git a/src/frontend/A32/translate/impl/thumb16.cpp b/src/frontend/A32/translate/impl/thumb16.cpp index d05a7255..34b0fc10 100644 --- a/src/frontend/A32/translate/impl/thumb16.cpp +++ b/src/frontend/A32/translate/impl/thumb16.cpp @@ -1002,7 +1002,7 @@ bool TranslatorVisitor::thumb16_BLX_reg(Reg m) { return UnpredictableInstruction(); } - ir.PushRSB(ir.current_location.AdvancePC(2)); + ir.PushRSB(ir.current_location.AdvancePC(2).AdvanceIT()); ir.UpdateUpperLocationDescriptor(); ir.BXWritePC(ir.GetRegister(m)); ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 2) | 1)); @@ -1013,9 +1013,9 @@ bool TranslatorVisitor::thumb16_BLX_reg(Reg m) { // SVC # bool TranslatorVisitor::thumb16_SVC(Imm<8> imm8) { const u32 imm32 = imm8.ZeroExtend(); + ir.PushRSB(ir.current_location.AdvancePC(2).AdvanceIT()); ir.UpdateUpperLocationDescriptor(); ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 2)); - ir.PushRSB(ir.current_location.AdvancePC(2)); ir.CallSupervisor(ir.Imm32(imm32)); ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}}); return false; diff --git a/src/frontend/A32/translate/impl/thumb32_branch.cpp b/src/frontend/A32/translate/impl/thumb32_branch.cpp index ca0b35eb..378f6102 100644 --- a/src/frontend/A32/translate/impl/thumb32_branch.cpp +++ b/src/frontend/A32/translate/impl/thumb32_branch.cpp @@ -16,7 +16,7 @@ bool TranslatorVisitor::thumb32_BL_imm(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1> j return UnpredictableInstruction(); } - ir.PushRSB(ir.current_location.AdvancePC(4)); + ir.PushRSB(ir.current_location.AdvancePC(4).AdvanceIT()); ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1)); const s32 imm32 = static_cast((concatenate(S, i1, i2, hi, lo).SignExtend() << 1) + 4); @@ -40,7 +40,7 @@ bool TranslatorVisitor::thumb32_BLX_imm(Imm<1> S, Imm<10> hi, Imm<1> j1, Imm<1> return UnpredictableInstruction(); } - ir.PushRSB(ir.current_location.AdvancePC(4)); + ir.PushRSB(ir.current_location.AdvancePC(4).AdvanceIT()); ir.SetRegister(Reg::LR, ir.Imm32((ir.current_location.PC() + 4) | 1)); const s32 imm32 = static_cast(concatenate(S, i1, i2, hi, lo).SignExtend() << 1); diff --git a/src/frontend/A32/translate/impl/thumb32_control.cpp b/src/frontend/A32/translate/impl/thumb32_control.cpp index d13111c7..9c192ca3 100644 --- a/src/frontend/A32/translate/impl/thumb32_control.cpp +++ b/src/frontend/A32/translate/impl/thumb32_control.cpp @@ -93,11 +93,13 @@ bool TranslatorVisitor::thumb32_MSR_reg(bool write_spsr, Reg n, Imm<4> mask) { ir.SetGEFlagsCompressed(ir.And(value, ir.Imm32(0x000F0000))); } } else { + ir.UpdateUpperLocationDescriptor(); + const u32 cpsr_mask = (write_nzcvq ? 0xF8000000 : 0) | (write_g ? 0x000F0000 : 0) | 0x00000200; const auto old_cpsr = ir.And(ir.GetCpsr(), ir.Imm32(~cpsr_mask)); const auto new_cpsr = ir.And(value, ir.Imm32(cpsr_mask)); ir.SetCpsr(ir.Or(old_cpsr, new_cpsr)); - ir.PushRSB(ir.current_location.AdvancePC(4)); + ir.PushRSB(ir.current_location.AdvancePC(4).AdvanceIT()); ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4)); ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}}); return false; diff --git a/src/frontend/A32/translate/impl/vfp.cpp b/src/frontend/A32/translate/impl/vfp.cpp index c2accb63..ea47eaa4 100644 --- a/src/frontend/A32/translate/impl/vfp.cpp +++ b/src/frontend/A32/translate/impl/vfp.cpp @@ -1137,8 +1137,9 @@ bool TranslatorVisitor::vfp_VMSR(Cond cond, Reg t) { } // TODO: Replace this with a local cache. - ir.PushRSB(ir.current_location.AdvancePC(4)); + ir.PushRSB(ir.current_location.AdvancePC(4).AdvanceIT()); + ir.UpdateUpperLocationDescriptor(); ir.SetFpscr(ir.GetRegister(t)); ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4)); ir.SetTerm(IR::Term::PopRSBHint{});