diff --git a/src/backend/x64/emit_x64_floating_point.cpp b/src/backend/x64/emit_x64_floating_point.cpp
index 2321b77b..b710a989 100644
--- a/src/backend/x64/emit_x64_floating_point.cpp
+++ b/src/backend/x64/emit_x64_floating_point.cpp
@@ -920,6 +920,10 @@ static void EmitFPRSqrtEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* i
     code.CallFunction(&FP::FPRSqrtEstimate<FPT>);
 }
 
+void EmitX64::EmitFPRSqrtEstimate16(EmitContext& ctx, IR::Inst* inst) {
+    EmitFPRSqrtEstimate<u16>(code, ctx, inst);
+}
+
 void EmitX64::EmitFPRSqrtEstimate32(EmitContext& ctx, IR::Inst* inst) {
     EmitFPRSqrtEstimate<u32>(code, ctx, inst);
 }
diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp
index 27527f6c..86d9923c 100644
--- a/src/frontend/ir/ir_emitter.cpp
+++ b/src/frontend/ir/ir_emitter.cpp
@@ -1967,11 +1967,18 @@ U16U32U64 IREmitter::FPRoundInt(const U16U32U64& a, FP::RoundingMode rounding, b
     }
 }
 
-U32U64 IREmitter::FPRSqrtEstimate(const U32U64& a) {
-    if (a.GetType() == Type::U32) {
+U16U32U64 IREmitter::FPRSqrtEstimate(const U16U32U64& a) {
+    switch (a.GetType()) {
+    case Type::U16:
+        return Inst<U16>(Opcode::FPRSqrtEstimate16, a);
+    case Type::U32:
         return Inst<U32>(Opcode::FPRSqrtEstimate32, a);
+    case Type::U64:
+        return Inst<U64>(Opcode::FPRSqrtEstimate64, a);
+    default:
+        UNREACHABLE();
+        return U16U32U64{};
     }
-    return Inst<U64>(Opcode::FPRSqrtEstimate64, a);
 }
 
 U32U64 IREmitter::FPRSqrtStepFused(const U32U64& a, const U32U64& b) {
diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h
index 09935cf6..27b02776 100644
--- a/src/frontend/ir/ir_emitter.h
+++ b/src/frontend/ir/ir_emitter.h
@@ -309,7 +309,7 @@ public:
     U16U32U64 FPRecipExponent(const U16U32U64& a);
     U32U64 FPRecipStepFused(const U32U64& a, const U32U64& b);
     U16U32U64 FPRoundInt(const U16U32U64& a, FP::RoundingMode rounding, bool exact);
-    U32U64 FPRSqrtEstimate(const U32U64& a);
+    U16U32U64 FPRSqrtEstimate(const U16U32U64& a);
     U32U64 FPRSqrtStepFused(const U32U64& a, const U32U64& b);
     U32U64 FPSqrt(const U32U64& a);
     U32U64 FPSub(const U32U64& a, const U32U64& b, bool fpcr_controlled);
diff --git a/src/frontend/ir/microinstruction.cpp b/src/frontend/ir/microinstruction.cpp
index a7c3386e..f7545b3d 100644
--- a/src/frontend/ir/microinstruction.cpp
+++ b/src/frontend/ir/microinstruction.cpp
@@ -282,6 +282,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
     case Opcode::FPRoundInt16:
     case Opcode::FPRoundInt32:
     case Opcode::FPRoundInt64:
+    case Opcode::FPRSqrtEstimate16:
     case Opcode::FPRSqrtEstimate32:
     case Opcode::FPRSqrtEstimate64:
     case Opcode::FPRSqrtStepFused32:
diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc
index c7a4c227..0da852cb 100644
--- a/src/frontend/ir/opcodes.inc
+++ b/src/frontend/ir/opcodes.inc
@@ -501,6 +501,7 @@ OPCODE(FPRecipStepFused64,                                  U64,            U64,
 OPCODE(FPRoundInt16,                                        U16,            U16,            U8,             U1                              )
 OPCODE(FPRoundInt32,                                        U32,            U32,            U8,             U1                              )
 OPCODE(FPRoundInt64,                                        U64,            U64,            U8,             U1                              )
+OPCODE(FPRSqrtEstimate16,                                   U16,            U16                                                             )
 OPCODE(FPRSqrtEstimate32,                                   U32,            U32                                                             )
 OPCODE(FPRSqrtEstimate64,                                   U64,            U64                                                             )
 OPCODE(FPRSqrtStepFused32,                                  U32,            U32,            U32                                             )