From 6fc9e127fe90077a8a3f3ceae5f8c72659cb929e Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Mon, 9 Jul 2018 17:25:13 -0400
Subject: [PATCH] simd_scalar_two_register_misc: Handle 64-bit case in SCVTF
 and UCVTF's scalar double/single-precision variant

Avoids falling back to the interpreter in the 64-bit case.
---
 .../A64/translate/impl/simd_scalar_two_register_misc.cpp      | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
index 5bb8f28b..fd770dbe 100644
--- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
+++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
@@ -40,7 +40,7 @@ bool TranslatorVisitor::SCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
     if (esize == 32) {
         element = ir.FPS32ToSingle(element, false, true);
     } else {
-        return InterpretThisInstruction();
+        element = ir.FPS64ToDouble(element, false, true);
     }
     V_scalar(esize, Vd, element);
     return true;
@@ -53,7 +53,7 @@ bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
     if (esize == 32) {
         element = ir.FPU32ToSingle(element, false, true);
     } else {
-        return InterpretThisInstruction();
+        element = ir.FPU64ToDouble(element, false, true);
     }
     V_scalar(esize, Vd, element);
     return true;